Anik Srivastava

CEO

Pflugerville, Texas, United States11 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 9 years of experience in Embedded Memory IP design.
  • Led teams to deliver multiple high-performance memory products.
  • Expert in custom SRAM design and verification.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Embedded Memory and VLSI technologies.

Contact

Skills

Core Skills

Embedded Memory DesignCustom Memory DesignTiming AnalysisAutomationMemory DesignVerificationProduct DeliveryDesign VerificationCompiler DesignData Analysis

Other Skills

BashCC++CMOSCommunicationDigital ElectronicsEagle PCBElectronicsEmbedded SystemsFinfetHTMLJavaJavaScriptMOSMatlab

About

Custom SRAM Design Engineer at Qualcomm with an MS in Electrical engineering from the University of Minnesota - Twin Cities. High achiever with a mix of technical and leadership skills spanning Circuit design, RTL verification and Memory Compiler delivery. 9 years of experience in Embedded Memory IP design on cutting edge technologies. Worked as a custom SRAM designer for Apple Inc, and as a Technical Leader at STMicroelectronics and an R&D Engineer at Synopsys, successfully delivering products to major semiconductor companies such as Apple, Samsung, TSMC, Hisilicon and AMD. I am passionate about my work and enjoy working in a team. I come up with new ideas about the projects I work on and figure out ways to optimize and improve the workflow and operations. I view my responsibilities in tandem with the business goals to meet the targets and aggressive deadlines. I plan my duties effectively and help in setting internal deadlines with the team. Completed my B.E. in Electronics and Communication from NSIT, Delhi University in Jun 2013. I have good communications skills and proficiency in Electronic circuit design, simulators, C/C++ programming languages, shell scripting.

Experience

Qualcomm

2 roles

SRAM Senior Staff Engineer

Promoted

Nov 2024Present · 1 yr 4 mos · Austin, Texas, United States · Hybrid

  • Custom memories for the Nuvia CPU cores.
  • SnapdragonX Elite line.
  • Multi port Data Cache macro design for performance and efficienct cores.
  • Spice | Nanotime | Liberate | Solido | Totem | Reliability | CAD

Staff Engineer

Mar 2022Nov 2024 · 2 yrs 8 mos · Austin, Texas, United States · Hybrid

  • Custom memories for the Nuvia CPU cores.
  • SnapdragonX Elite line.
  • Multi port Data Cache macro design for performance and efficienct cores.
  • Implemented a new python based spice internal timing flow, and also the at-speed tight stimulus flow with superior, actionable summary reports.
  • Adept in Solido tools such as Solido Design Environment for variation analysis, SolidoChar for library interpolation and Validate for library file quality assurance.
CommunicationTest Automation ToolsSchematic CapturePath FindingPresentationsTransistors+2

Apple

SRAM Design Engineer

Feb 2020Mar 2022 · 2 yrs 1 mo · Cupertino, California, United States

  • Custom high performance, low power Memory Design, Verification and Production.
CommunicationTest Automation ToolsSchematic CapturePath FindingPresentationsTransistors+2

Samsung electronics

Circuit Design Intern

May 2019Dec 2019 · 7 mos · Austin, Texas Area

CommunicationTest Automation ToolsSchematic CapturePath FindingPresentationsTransistors

Stmicroelectronics

Technical Leader

Dec 2017Aug 2018 · 8 mos · Greater Noida

  • Product delivery; Product design; Reliability analysis; Design Verification
  • Worked on and verified temperature adaptive Read assist circuitry to improve Read stability
  • Balanced read assist impact perfectly on either side of a butterfly architecture
  • Verified several memory compilers for Aging degradation including HCI/BTI and TDDB
  • Designed custom instances with area reduction and simultaneous significant performance improvement.
  • Maxwell, Virtuoso, Eldo, XA, Hspice, StarRC
CommunicationTest Automation ToolsSchematic CapturePath FindingPresentationsTransistors+2

Synopsys inc

2 roles

R&D Engineer II

Promoted

Mar 2016Nov 2017 · 1 yr 8 mos · Noida Area, India

  • Product delivery; Customer Engagement; Product Design; Automation
  • Embedded Memory (SRAM) design.
  • Successfully led a team of 3, delivered 3 products in 4 months.
  • Successfully delivered Ultra High Density RF compiler.
  • Led a 7nm Ultra High Density High Speed SRAM compiler (Pseudo dual port).
  • Validated memory compilers using Synopsys NanoTime tool.
  • Optimized setup/hold timings on urgent client request in 15 days, with minimal design changes
  • Assisted in team project planning, scheduling and project status consolidation for sub-teams
  • Added periphery off enable feature onto an existing memory compiler
  • Improved cycle and access times by 25% for high speed product on 10nm, without reliability loss
  • Worked on compiler placement file/tiler and cleaned VXL, ESPCV
CommunicationTest Automation ToolsSchematic CapturePath FindingPresentationsTransistors+2

R&D Engineer

Jun 2013Feb 2016 · 2 yrs 8 mos · Noida Area, India

  • Product Design; Data Analysis; Automation
  • Embedded Memory (SRAM) Design.
  • Worked on the latest Nano-technology nodes 16nm, 14nm, 10nm.
  • Designed digital logic circuits, and ensured functionality for very high silicon yields.
  • Optimized logic for high speed (30% improvement) as well as low leakage (10% reduction) operations to meet aggressive targets.
  • Quality Assurance on final products to ensure proper operation for a wide range of customer requirements and environments.
  • Automated several data analysis processes using shell scripting to get better results in lesser time.
  • Mentored 4 new additions to the team.
  • Worked on Timing/Power margins, Read/Write Margins, Spice stimulus, measurements, characterization.
CommunicationTest Automation ToolsSchematic CapturePath FindingPresentationsTransistors+2

Stmicroelectronics

Intern

Nov 2012May 2013 · 6 mos

  • Design a crystal oscillator with Pierce Architecture
  • Convert the oscillator equations and setup into an algorithm.
  • Use C and MATLAB to simulate the oscillator and predict amplitude.
  • Keep error within 5%.
Transistors

Appin technology lab

Intern

Jun 2011Jul 2011 · 1 mo · New Delhi Area, India

  • Studied 8051 ucontroller, embedded systems and robotics.
  • Various projects using 8051 completed.
  • Line Follower Bot
  • Obstacle Avoider
  • RF controlled small car
  • DTMF controlled led patterns
  • Awarded merit certificate.

Education

University of Minnesota

Master of Science - MS — Electrical Engineering (VLSI)

Jan 2018Jan 2019

NSIT

Bachelor of Engineering (B.E.) — Electronics and Communications Engineering

Jan 2009Jan 2013

Green Fields School

High School — Computer Science

Jan 1997Jan 2009

Stackforce found 100+ more professionals with Embedded Memory Design & Custom Memory Design

Explore similar profiles based on matching skills and experience