Miten Chotaliya

Software Engineer

Austin, Texas, United States12 yrs 3 mos experience
Highly Stable

Key Highlights

  • Expert in DFT methodologies and ATPG techniques.
  • Proven track record in integrated circuit design.
  • Strong background in simulation and debugging.
Stackforce AI infers this person is a DFT and IC design expert in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

DftAtpg

Other Skills

BISTBoundary ScanIntegrated Circuit DesignJTAGNCSimPLLRTL designScan InsertionSimulationSimulationsStatic Timing AnalysisVerilog

Experience

Arm

Senior DFT Engineer

Feb 2024 – Present · 2 yrs 1 mo · Austin, Texas, United States · On-site

Ashley tech solutions

Lead DFT Engineer

Nov 2023 – Feb 2024 · 3 mos · California, United States

Eximius design

2 roles

Technical Lead, DFT

Promoted

Jan 2023 – Nov 2023 · 10 mos

Staff Engineer, DFT

Oct 2018 – Dec 2022 · 4 yrs 2 mos

Einfochips

Senior DFT Engineer

Mar 2016 – Oct 2018 · 2 yrs 7 mos · Ahmedabad, India

Sicon design technologies pvt. ltd.

DFT Engineer

Nov 2013 – Mar 2016 · 2 yrs 4 mos · Bangalore

Stmicroelectronics

DFT Engineer

Jul 2012 – May 2013 · 10 mos · Noida Area, India

  • Project : “Development of DFT for TMC IP in SoC"
  • Description :
  • Made the understanding on DFT basics,Techniques : Scan, ATPG and Boundary Scan/JTAG.
  • Ramped up with ATPG Flow & shell/perl/tcl scripting.
  • Hands on & responsible for ATPG pattern Generation & simulation of Stuck at and Transition fault models.
  • Worked on Simulation debug for ATPG patterns and analysis on BSD sims. Also, performed simulation of memory BIST with and without PLL, BITMAP tests and verifying the bend and bbad signals of the same.
  • Additionally Learned synopsys/custom OCC used for SoC IP.
ATPGDFTBoundary ScanJTAGSimulationBIST

Education

Institute of technology,NU Nirma University

M.Tech — VLSI Design

Ahmedabad Institute of Technology Gujarat University

B.E — Electronics & communication

Jan 2010 – Present

GATE-2011

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