Sagar Kataria

Software Engineer

Bengaluru, Karnataka, India14 yrs 10 mos experience

Highly Stable

Key Highlights

5 years of experience in SoC Design-for-Test engineering.
Expertise in DFT for automotive microcontrollers.
Proficient in implementing ASIL-D safety requirements.

Stackforce AI infers this person is a semiconductor design engineer with a focus on DFT and safety compliance.

Contact

Skills

Core Skills

DftDfxVerification

Other Skills

ASICATPGApplication-Specific Integrated Circuits (ASIC)Automatic Test Pattern Generation (ATPG)CC++DRCDebuggingDesign Rule Checking (DRC)EDAEmbedded SystemsICIntegrated Circuit DesignIntegrated Circuits (IC)JTAG

About

Overall 5 year experience as SoC Design-for-Test (DFT) engineer. Worked on Automotive microcontrollers for Power Train & Safety, ADAS Applications SOCs involving ASIL-D (ISO26262) level Safety Requirements for DFT which involved various on-chip Self Tests

Experience

Google

DFT Engineer

Jun 2022 – Present · 3 yrs 9 mos · Bengaluru, Karnataka, India

Qualcomm

2 roles

Staff Engineer

Dec 2020 – Jun 2022 · 1 yr 6 mos

Lead Engineer, Sr.

Aug 2017 – Dec 2020 · 3 yrs 4 mos

Intel corporation

DFX Design Engineer

Oct 2015 – Aug 2017 · 1 yr 10 mos · Bengaluru Area, India

Freescale semiconductor

Senior Design Engineer-DFT

Jun 2011 – Oct 2015 · 4 yrs 4 mos · Noida Area, India

Experience includes:
DFT Architect: Overall DFT clocking implementation for various modes, DFT control logic insertion at RTL, DFT blocks integration
SCAN: Scan design implementation, Compression analysis, Scan Insertion, ATPG, Coverage and DRC Analysis
LBIST: LogicBIST insertion and verification at RTL and Gate Level, LogicBIST related netlist flows
MBIST implementation and verification
Boundary scan: Design implementation, BSDL generation and verification
DFT STA clock definition and constraint development, assessing timing reports and exceptions.
Verification: Verification of DFT logic at RTL and Gate level, Verification of ATPG patterns and debug.
Analog and Functional Test Architecture Development: Worked towards parallelism in functional test modes, Test Pin Muxing for different modes, test access mechanism for functional block testing.
Worked extensively on Spyglass DFT checks at SoC and IP level, static and dynamic design checks using Assertions Based Verification
Worked extensively on developing design flow methodologies and automation.
Skills: Verilog, SystemVerilog, Perl, TCL