Dec 2011 – Mar 2012 · 3 mos · Noida

• Worked on the development of Talus Design (the Synthesis Tool) specially the congestion based remapping.

Feb 2010 – Dec 2011 · 1 yr 10 mos · Hyderabad Area, India

• Working on the development of a Performance Analysis tool for Windows Phone (called WP7 Profiler). This tool can be used to evaluate and improve (i.e. profile) the performance of Windows Phone applications. The Performance Analysis tool is installed as part of the Windows Phone SDK. It is fully integrated into Visual Studio.

May 2004 – Feb 2010 · 5 yrs 9 mos · Noida Area, India

• Worked on the development of Cadence's Logic Synthesis tool named RC (RTL Compiler). RC reads in a high level hardware description(HDL) (usually written in Verilog/VHDL) and generates an optimized logic gates representation (netlist). I am part of the Frontend Team which is responsible for developing the frontend of the tool i.e. it used to read and interpret the given HDL design, create CDFGs and inferring generic gate level netlist. I also worked on another Synthesis Tool named BG (BuildGates). In addition, I also worked on interesting projects like IP Protection, QoR improving transforms, core data-structure level projects etc.

Aug 2002 – May 2004 · 1 yr 9 mos · New Delhi Area, India

• Worked on the Design/Developement of Telecommunication Systems. Worked on the MAP and TCAP layers of the SS7 protocol stack at the MSC (Mobile Switching centre) and SMSC (Short Message Service Centre)