Shireesh Agrawal

CTO

Bengaluru, Karnataka, India13 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Functional Verification and UVM methodologies.
Proven experience in ASIC and RTL Verification.
Strong background in Digital Electronics and System Verification.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC design and verification methodologies.

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Skills

Core Skills

Functional VerificationUvm

Other Skills

Open Verification MethodologyDigital ElectronicsSystem VerificationVerilogAssertion Based VerificationAssertionsAXIOCPAMBA AHBASICRTL VerificationOOPVIPSimvisionNCSim

Experience

13 yrs 3 mos

Total Experience

3 yrs 3 mos

Average Tenure

7 yrs 5 mos

Current Experience

Qualcomm

Lead Engineer, Sr.

Nov 2018 – Present · 7 yrs 5 mos · Bengaluru, Karnataka, India · On-site

Functional VerificationUVMOpen Verification MethodologyDigital ElectronicsSystem VerificationVerilog+27

Synapse tecno design

Lead Engineer

Mar 2017 – Oct 2018 · 1 yr 7 mos

Intel corporation

Graphics Hardware Engineer

Jul 2015 – Jan 2017 · 1 yr 6 mos · Greater Bengaluru Area

Samsung r&d institute india bangalore

Senior Software Engineer

Jul 2012 – Apr 2015 · 2 yrs 9 mos · Bengaluru, Karnataka, India

Involved in Design and Development of Verication Environment for IP functional verication, environ-ment development, functional coverage and testplan development
High prociency with Verilog/System Verilog and UVM
Experience with protocols like OCP, AXI etc

VerilogSystem VerilogUVMOCPAXIFunctional Verification