Dibya Narayan Behera

Software Engineer

Bengaluru, Karnataka, India7 yrs 9 mos experience

Most Likely To Switch

Key Highlights

7+ years of experience in IP and SoC verification.
Expertise in System Verilog and UVM methodologies.
Proven track record with clients like Intel and AMD.

Stackforce AI infers this person is a Verification Engineer specializing in IP and SoC design verification.

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Skills

Core Skills

PcieCoverage AnalysisBlock-level VerificationUvm

Other Skills

Analytical SkillsRandomizationVerdiTestbench DevelopmentCRC CalculationFunctional CoverageAssertion-Based VerificationVerilogSystemVerilogUniversal Verification Methodology (UVM)SoCDigital ElectronicsApplication-Specific Integrated Circuits (ASIC)UnixLinux

About

Results-driven Verification Engineer with 7+ years of success ensuring high-quality IP and SoC designs for premier clients like Intel, AMD, LX Semicon, and LG. Proven expertise in designing and developing robust, reusable verification environments using HVL-based methodologies. Strong command of System Verilog and UVM, coupled with comprehensive knowledge of IP, block, and subsystem-level verification, including Gate Level Simulation (GLS). Adept at implementing System Verilog Assertions, driving functional and code coverage closure, and proficient in key bus protocols such as PCIe, AMBA AHB, and AXI. I am dedicated to delivering high-quality, bug-free IP and SoC designs through rigorous and meticulous verification.

Experience

7 yrs 9 mos

Total Experience

1 yr 3 mos

Average Tenure

2 yrs 3 mos

Current Experience

Amd

Senior Contract Engineer

May 2024 – Jun 2025 · 1 yr 1 mo · Penang, Malaysia · On-site

Synapse design inc.

Senior Lead Engineer

Jan 2024 – Present · 2 yrs 4 mos · Bengaluru, Karnataka, India · On-site

Wipro limited

Senior Project Engineer

Feb 2022 – Jul 2023 · 1 yr 5 mos · Bengaluru, Karnataka, India · Remote

Validating Features of PCIe at the SoC level.
Maintaining PCIe regression, debugging the failures, and fixing them.
Improving/adding the test/sequences as per the test plan/ customer requirements.
Running the regression locally with multiple seeds for finding the bugs, report the same to the Team Lead and the Customer as well along with the fix.

PCIeCoverage AnalysisAnalytical SkillsRandomizationVerdi

Tessolve

Design Engineer

Jan 2021 – Jan 2022 · 1 yr · Bangalore Urban, Karnataka, India

Project: Block Level Verification of Data Control for APDI Protocol
Description: Verification of Data control block captures the 10 bit raw data (Frame, Line and
Pixel Data) from the DUT, de-scrambles, calculates the CRC for each of the data and process
the calculated information to the SDL Data block which converts the 10 bit data to 8 bit data
and processed it to the next block.
Key Responsibilities:
 Core Skills Demonstrated: Block-Level Verification, UVM (implied by components),
Testbench Development, Reference Model Design, CRC Calculation, Functional Coverage,
Code Coverage, Assertion-Based Verification, Regression Management, Debugging, RTL Bug
Reporting (JIRA), Gate-Level Simulation (GLS), Netlist Debugging, SystemVerilog (implied)