PALLAVI ATHA — Product Engineer
11+ years of experience in Product Engineering, Application Engineering, Product Development Management, and Design and Verification Engineering in the Electronics Design Automation/Semiconductor industry. Strong in customer management, with expertise in identifying and solving customer problems by providing tailored solutions based on deep insights into their environments KEY SKILLS & EXPERTISE: • Formal Verification: Extensive experience in Formal Verification methodologies, including Verification Apps, Core Formal Verification using ABV, Hybrid Verification, and contributions to metrics-driven verification (Test Planning, Coverage Analysis, Sign-Off, Proof Convergence). • Hands-on experience with Formal Apps: Register Verification, Coverage Closure, X-check, Sequential Logical Equivalence Checking, Connectivity Verification, Security Verification, and Property Verification. • Proficient in analyzing and improving formal coverage metrics to assess proof completeness, identify coverage gaps, and optimize verification efficiency. • Knowledgeable in HDLs like Verilog and VHDL, as well as OO-HVLS (SystemVerilog). Proficient in OVM and UVM verification methodologies. • Skilled in EDA Tools: Questa Formal, Qnespin Formal Apps, QuestaSim, ModelSim, JasperGold, NCSim, Visualizer, and Xilinx ISE. • Proficient in scripting languages such as Shell, TclTk, and Perl. • Familiar with ISO standards in automotive and aerospace, including DO-254 and ISO 26262, as well as DO-254 tools flow for design assurance levels (DAL). • Expertise in technical documentation: End-user, product, and technical documentation, with experience in content management systems, DITA, and publishing & image editing tools. • Knowledge of protocols such as I2C, SPI, AMBA, AHB, ARBITER, SDRAM Controller, and UART. • Excellent communication skills (both written and verbal) and a quick learner with a strong ability to apply new technical concepts. TECHNICAL SKILLS: • Language: System Verilog, UVM, Verilog, VHDL, Basics of C++, Embedded C, XML, SVA, PSL • Software: ModelSim, QuestaSim, Questa Formal Apps, Qnespin Formal Apps, Visuailiser, HDL designer, ReqTracer, Xilinx Web Pack, NCSim, Jasper Gold • Scripting Language: Shell, Perl, Tcl TK • Project Management: JIRA, Confluence, Github • Cloud Services: AWS • Authoring Tools: Adobe Framemaker (structured & unstructured), Oxygen, MS Word, Adobe Acrobat Pro • Image& Video Editing Tool: Inkscape, Snagit, Adobe Photoshop, Corel Draw, BB Flashback Pro, Lumen5 AI
Stackforce AI infers this person is a Formal Verification Expert in the Electronics Design Automation industry.
Location: Bengaluru, Karnataka, India
Experience: 12 yrs 5 mos
Skills
- Formal Verification
- Customer Engagement
- System Verilog
- Verification
- Design Verification
Career Highlights
- Over 11 years in Electronics Design Automation.
- Expert in Formal Verification methodologies.
- Strong customer engagement and problem-solving skills.
Work Experience
Siemens EDA (Siemens Digital Industries Software)
Expert Product Engineer - Formal Verification (3 yrs 2 mos)
Lead Member Of Technical Staff - Formal Product Engineer (1 yr 2 mos)
Mentor Graphics
Application Engineer - FV (3 yrs 7 mos)
Information Developer (1 yr 7 mos)
Freescale Semiconductor
Contract Engineer - ASIC (1 yr 4 mos)
Tevatron Technologies Pvt. Ltd.
Design & Verification Engineer (1 yr 7 mos)
L&T Sargent & Lundy
INTERN (3 mos)
Education
Master of Technology (MTech) at SURESH GYAN VIHAR UNIVERSITY
Bachelor of Technology (BTech) at suresh gyan vihar university
at Army School Narangi , Kendriya Vidyalaya