PALLAVI ATHA

Product Engineer

Bengaluru, Karnataka, India12 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 11 years in Electronics Design Automation.
  • Expert in Formal Verification methodologies.
  • Strong customer engagement and problem-solving skills.
Stackforce AI infers this person is a Formal Verification Expert in the Electronics Design Automation industry.

Contact

Skills

Core Skills

Formal VerificationCustomer EngagementSystem VerilogVerificationDesign Verification

Other Skills

Code CoverageCoverage AnalysisDITA XMLDesign ImplementationDocumentationEDAElectronicsEmbedded SystemsFPGAField-Programmable Gate Arrays (FPGA)FrameMakerInkscapeLeadershipLinuxMatlab

About

11+ years of experience in Product Engineering, Application Engineering, Product Development Management, and Design and Verification Engineering in the Electronics Design Automation/Semiconductor industry. Strong in customer management, with expertise in identifying and solving customer problems by providing tailored solutions based on deep insights into their environments KEY SKILLS & EXPERTISE: • Formal Verification: Extensive experience in Formal Verification methodologies, including Verification Apps, Core Formal Verification using ABV, Hybrid Verification, and contributions to metrics-driven verification (Test Planning, Coverage Analysis, Sign-Off, Proof Convergence). • Hands-on experience with Formal Apps: Register Verification, Coverage Closure, X-check, Sequential Logical Equivalence Checking, Connectivity Verification, Security Verification, and Property Verification. • Proficient in analyzing and improving formal coverage metrics to assess proof completeness, identify coverage gaps, and optimize verification efficiency. • Knowledgeable in HDLs like Verilog and VHDL, as well as OO-HVLS (SystemVerilog). Proficient in OVM and UVM verification methodologies. • Skilled in EDA Tools: Questa Formal, Qnespin Formal Apps, QuestaSim, ModelSim, JasperGold, NCSim, Visualizer, and Xilinx ISE. • Proficient in scripting languages such as Shell, TclTk, and Perl. • Familiar with ISO standards in automotive and aerospace, including DO-254 and ISO 26262, as well as DO-254 tools flow for design assurance levels (DAL). • Expertise in technical documentation: End-user, product, and technical documentation, with experience in content management systems, DITA, and publishing & image editing tools. • Knowledge of protocols such as I2C, SPI, AMBA, AHB, ARBITER, SDRAM Controller, and UART. • Excellent communication skills (both written and verbal) and a quick learner with a strong ability to apply new technical concepts. TECHNICAL SKILLS: • Language: System Verilog, UVM, Verilog, VHDL, Basics of C++, Embedded C, XML, SVA, PSL • Software: ModelSim, QuestaSim, Questa Formal Apps, Qnespin Formal Apps, Visuailiser, HDL designer, ReqTracer, Xilinx Web Pack, NCSim, Jasper Gold • Scripting Language: Shell, Perl, Tcl TK • Project Management: JIRA, Confluence, Github • Cloud Services: AWS • Authoring Tools: Adobe Framemaker (structured & unstructured), Oxygen, MS Word, Adobe Acrobat Pro • Image& Video Editing Tool: Inkscape, Snagit, Adobe Photoshop, Corel Draw, BB Flashback Pro, Lumen5 AI

Experience

Siemens eda (siemens digital industries software)

2 roles

Expert Product Engineer - Formal Verification

Promoted

Jan 2023Present · 3 yrs 2 mos

  • Formal Product Development & Support: Lead the development, technical marketing, and customer support for Questa Formal Verification products.
  • Lead Product Engineer (PE) for Formal Test Planning & Coverage Analysis tools (Such as Covercheck, Formal Coverage, merging UCDB, VIQ etc) focusing on enhancing product features and capabilities. Roadmap & integration of apps.
  • Product Feature Definition: Capture requirements, define methodologies, and drive the product rollout for next-generation formal verification products and solutions.
  • Customer Engagement: Lead customer engagements through AEs for India & APAC region for Questa Formal Apps. Directly engage with customers during product evaluations to ensure milestones are met. Provide customer support through product demonstrations, training, evaluations, and competitive benchmarking.
  • Questa Formal Consulting Ownership: Own and manage Formal Consulting projects for customers, ensuring successful planning, strategy, execution and delivery of customized solutions mainly verifying complex designs using hybrid formal & simulation methods to meet their specific needs
  • Troubleshooting & Debugging: Resolve technical challenges using advanced debugging techniques to address inconclusive proofs and optimize proof convergence.
  • Collaboration with Sales & Account Teams: Work closely with sales management and account teams to understand business opportunities and customer needs.
  • Global Collaboration: Work with global development teams, product managers, and business centers to maintain and update end-user and system administration documentation.
  • Support Early Field Deployments: Participate in the testing of new products, interoperability testing, and the execution of test plans, test procedures, and test cases.
  • Customer Feedback & Roadmap Development: Consolidate customer feedback and provide insights to product managers for roadmap recommendations, feature prioritization, and new product initiatives.
Formal VerificationTest PlanningCoverage AnalysisCustomer EngagementTechnical Documentation

Lead Member Of Technical Staff - Formal Product Engineer

Oct 2021Dec 2022 · 1 yr 2 mos

Mentor graphics

2 roles

Application Engineer - FV

Promoted

Apr 2018Nov 2021 · 3 yrs 7 mos

Information Developer

Aug 2016Mar 2018 · 1 yr 7 mos

Freescale semiconductor

Contract Engineer - ASIC

Mar 2015Jul 2016 · 1 yr 4 mos · Noida Area, India · On-site

  • Worked on I2C, SPI protocol in MCU department using System Verilog
  • Create Verification plan and develop SV based verification tests
  • Develop SV/UVM monitors to measure performance and improve Verification Environment
  • Influence R&D or product group to meet customer's needs and shape product direction.
  • Develop test environments using System Verilog based tests to achieve verification goals.
  • Edit technical documents and prepare them for publishing per guidelines established by the group.
  • General and detailed publication duties, responsible for global publishing in Freescale Web Page in Microcontrollers Unit (MPU)
  • Offload writers in the group by assisting with technical updates in XML source documents for Freescale devices such as Reference Manuals, Datasheets, and Product Briefs. Work to standardised processes and workflows in a cross-functional team environment.
  • Collaborate globally with program management, engineering, validation, and support across different countries including US, China, and the Czech Republic.
  • Work in compliance with corporate process and identity standards. Adhere to department style guidelines.
System VerilogVerification PlanSV/UVM MonitorsTechnical DocumentationVerification

Tevatron technologies pvt. ltd.

Design & Verification Engineer

Jun 2013Jan 2015 · 1 yr 7 mos · Noida Area, India

  • JOB ROLE:
  • Designing and implementing various design units proposed by Vendor and implementing over FPGA (Team Role)
  • Responsible for developing verification environment test benches, monitors and score-board test cases, RTL & gate netlist verification.
  • Handling Project details from the vendor as a Technical Marketing Engineer
  • Executed project’s Documentation in form of White papers
Design ImplementationVerification EnvironmentDocumentationDesign Verification

L&t sargent & lundy

INTERN

Apr 2012Jul 2012 · 3 mos · VADODARA INDIA

Education

SURESH GYAN VIHAR UNIVERSITY

Master of Technology (MTech) — VLSI

Jan 2012Jan 2013

suresh gyan vihar university

Bachelor of Technology (BTech)

Jan 2008Jan 2012

Army School Narangi , Kendriya Vidyalaya

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