Nov 2016 – Jan 2019 · 2 yrs 2 mos · Bengaluru Area, India

Sep 2014 – Nov 2016 · 2 yrs 2 mos · Bangalore

• Worked as a DFT consultant for Texas Instruments

Oct 2010 – Sep 2014 · 3 yrs 11 mos · Ahmedabad Area, India

• 4.1 years of experience in Design for Testing (DFT) Domain in VLSI
• Worked on scan Insertion using synopsys DC compiler tool in one project
• Worked on formal verificatioin using synopsys formality tool in one project
• Worked on ATPG (Legacy and Compress mode) for stuck at, transition, Iddq, Path delay and small delay defect using synopsys tetramax tool in 4 chips (28nm and multimillion gate design)
• Worked on ATPG pattern validation ( Legacy and Compress mode) for stuck at, transition, Iddq, Path delay and small delay defect using synopsys tool VCS and Verdi in 4 chips (28nm and multimillion gate design)
• Worked on ATPG pattern validation (Legacy and Compress mode) for stuck at and Transition using cadence ncsim and simvision in one project.
• Worked on Tester (Agilent 93000) support and Post silicon debug for ATPG patterns in 3 chips (28nm and multimillion gate design)
• Worked on IO testing using IEEE 1149.1 and IEEE 1149.6 JTAG standard in 4 (28nm) chips
• Worked on MISC testing using IEEE 1687 IJTAG standard in 4 (28nm) chips
• Worked on Hierarchical ATPG and wrapper chain verification using IEEE 1500 standards in 2 (28nm) chips
• Worked on Power Aware ATPG in one chip
• Worked on Hierarchical Shared Codec architecture in One chip
• Worked on timing simulation of ATPG pattern in two chips
• Worked on MBIST insertion and validation using client specific tool in one project
• Worked on LBIST pattern validation using client specific tool in one project
• Worked on Synopsys OCC controller
• Good knowledge of synopsys compressor architecture and compress mode debug
• Good knowledge of cadence compressor architecture and compress mode debug
• Sound knowledge of Synthesis and STA
• Good knowledge of scripting in perl
• Good knowledge of C,C++, MATLAB, Verilog and System Verilog