Nandagopal P J

CEO

Bengaluru, Karnataka, India27 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

20 years of ASIC Verification experience
Led a 125 member team in front end verification
Delivered products for NASDAQ trading systems

Stackforce AI infers this person is a Semiconductor and Fintech expert with extensive ASIC verification and product development experience.

Contact

Skills

Core Skills

AsicVerificationFront End VerificationCustomer InteractionFpgaTestingProduct DevelopmentSoftware DevelopmentSystem TestingNetwork Switch TestingAsic Design

Other Skills

ValidationEmulationEnd-to-end product developmentResource augmentationArchitectureRTL designPacket processingFPGA synthesisSoftware QA testingC++Performance testingTest bench developmentDSPEmbedded SystemsProgramming

About

Twenty years of ASIC Verification experience with 12 years in product company and 8 years in service industry. Currently responsible for 125 member team, hiring, training, team deployment, turnkey project execution, customer interaction for business and team engagement. Responsible for functional verification, emulation, validation. Delivered products Ethernet L2 Network Switch, Low latency platform for Automated trading system for NASDAQ, Complex AXI based NoC Interconnect verificatoin, Queue manager with Ethernet & DDR3, Semantic Network processor with Custom CPU with lexer, parser and rule engine, Voice Over IP with RISC & DSP Processor with audio codecs. Worked on IP/Block level, Sub system / Cluster level, SoC level Verification, CPU Sub system verification. Familiar protocols like: Ethernet 1G/10G, DDR3, AMBA AHB, AXI, ARM Cortex CPU, RISC CPU, DSP processor, I2C, SPI, JTAG. Languages, Methodology used: Verilog, System Verilog, VHDL, UVM, C, Shell Script

Experience

27 yrs 9 mos

Total Experience

4 yrs 7 mos

Average Tenure

8 yrs 3 mos

Current Experience

Cientra

Verification Director

Feb 2018 – Present · 8 yrs 3 mos · Bengaluru Area, India

- Responsible for 125 member team in front end Verification, Validation, Emulation.

ASICVerificationValidationEmulation

Eximius design

Associate Director of Engineering

Mar 2015 – Feb 2018 · 2 yrs 11 mos · Bengaluru Area, India

Built 100 member team on front end verification.
Handled customer interactions for business development and opportunities and interact with customers for understanding project technical requirements and supporting customers with team skill.
Handled all three modes of work - end-to-end product development with interaction with different functional team, handling ODC/turnkey projects, helping customer with team support and resource augmentation.

Front end verificationCustomer interactionEnd-to-end product developmentResource augmentation

Concept2silicon systems

Senior ASIC Front end Manager

Apr 2011 – Mar 2015 · 3 yrs 11 mos · Bangalore India

Responsible for building and leading front end team of 25 members for customer service and customer product development
Responsible for building Tabula customer account for FPGA based IP & product developments
(1) Developed products for customer on Queue Manager with Ethernet 40G with DDR3 termination solution, responsible for architecture, RTL design, verification and porting in FPGA.
(2) Ethernet Sub system verification including 40G, 100G, 10G, 1G with auto negotiation, responsible for testing L2/L3 packet processing engine, MAC testing, PHY testing
(3) DDR3 subsystem verification with FPGA synthesis
Responsible for emulation platform test bench development for OCP Interconnect with ARM processor based verification for Bangalore based customer
Responsible for VIP development on AXI, AHB for AXI-AHB Bridge testing

FPGAVerificationArchitectureRTL design

Xambala

Engineering Manager

Dec 2003 – Feb 2011 · 7 yrs 2 mos · Chennai Area, India

Responsible for ASIC front end group, Software QA testing group leading 30 members
Built product Semantic processor for XML Parsing and XPath evaluation - CPU re-design with Lexer, Parser and Rule engine. Multiple RISC processor with Ethernet 10G traffic with DDR.
Built product for Automated trading system with ultra low latency platform for processing NASDAQ ITCH data and placing orders at OUCH. Involved in FPGA prototyping of product and System level testing with hardware board, C++ software testing for trading algorithm
Deployed the product in NASDAQ center and worked with traders for product performance tuning.

ASICSoftware QA testingProduct development

Intel

Senior Member Technical Staff

Mar 2002 – Nov 2003 · 1 yr 8 mos · Bengaluru Area, India

Responsible for Network Switch Testing
L2 Switch data path testing with performance testing
Switch features: Mirroring, QoS, head tail flow control, link aggregation, stacking, Control path L2 look up, vlan look up, etc
Involved in test bench in Specman E and testing the switch

Network Switch TestingPerformance testingTest bench development

Realchip

Senior Verification Lead

May 1998 – Mar 2002 · 3 yrs 10 mos · Chennai Area, India

Responsible for building and leading 20 member team with front end ASIC design and verification.
Built Voice Over IP VOIP Product - Developed Carmel DSP Sub system with two Lexra RISC Processor with Ethernet 1G, PCIX, USB, UART, GPIO, Audio codecs. Entire system works on time division multiplexing.
Involved in all phases of product development from design micro arch of DSP Sub system, RTL coding on DDR/SRAM memory controller, Verification of block level and later complete owning & responsible for full chip SoC Level testing with leading 15 member team.

ASIC designVerificationDSP