K

Karthikeyun Srinivasan

DevOps Engineer

India21 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Power Management for chiplet-based SoCs.
  • Led verification signoff for robust silicon bring-up.
  • Published technical papers at AATC.
Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on Power Management and Design Verification.

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Skills

Core Skills

Power ManagementDesign Verification

Other Skills

Design for DebugCache Resident Self-Test (CReST)Clock ManagementReset ManagementFuses ManagementCore Power ManagementData Fabric Power ManagementSystem-wide Power ManagementTest PlanningEmulationFirmware ValidationVerilog

About

• • Expertise in Power Management, Design for Debug, and Cache Resident Self-Test (CReST) for chiplet-based SoCs. • Proficient in Clock, Reset, Fuses, Core & Data Fabric Power Management, and System-wide Power Management. • Led SoC reset and boot-up verification signoff, ensuring robust silicon bring-up. • Defined verification strategies, collaborated with IP and architecture teams to establish project milestones. • Spearheaded test plan reviews for Power Management, Data Path, and Reset functionality of server SoCs. • Design Verification Lead for AMD's multi-chiplet module (CPU + Graphics). • Directed Emulation teams to accelerate boot code validation, reducing turnaround time. • Coordinated Platform Emulation and Firmware validation before tape-out. • Enabled ATE teams to achieve first-time-right silicon patterns, significantly cutting tester costs. • Key debug expert for functional and CReST silicon issues in AMD Server SoCs. • Published two technical papers at AATC (2017, 2022); one selected as a poster. • Mentored engineers, fostering career growth and technical excellence. • Innovated verification methodologies to streamline development cycles. • Collaborated globally to reduce verification complexity without compromising functionality.

Experience

21 yrs 4 mos
Total Experience
11 yrs 1 mo
Average Tenure
16 yrs 3 mos
Current Experience

Amd

2 roles

Principal Member Of Technical Staff

Promoted

Jun 2022Present · 3 yrs 10 mos

Senior Member Of Technical Staff

Jan 2010Jun 2022 · 12 yrs 5 mos

  • Server SoC Technical Lead for Power Management, Design for Debug and CReST(Cache Resident Self Test) functions
  • Design Verification Lead for AMD’s(CPU + GRAPHICS) multi chiplet module
  • Knowledge of Clock, Reset, Fuses, Core Power Management, Data Fabric Power Management and System wide Power Management
  • Work with the ATE team to deliver the Test patterns for CReST/AVFS and support the post silicon bring up activity
Power ManagementDesign for DebugCache Resident Self-Test (CReST)Clock ManagementReset ManagementFuses Management+4

Integrated device technology inc

Design Engineer

Dec 2004Dec 2010 · 6 yrs

  • ASIC Verification Engineer with progressive experience and involved in successful tape out of 3 PCIExpress Devices

Education

University of Westminster

Master of Science - MS — VLSI System Design

Jan 2002Jan 2004

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