Karthikeyun Srinivasan — DevOps Engineer
• • Expertise in Power Management, Design for Debug, and Cache Resident Self-Test (CReST) for chiplet-based SoCs. • Proficient in Clock, Reset, Fuses, Core & Data Fabric Power Management, and System-wide Power Management. • Led SoC reset and boot-up verification signoff, ensuring robust silicon bring-up. • Defined verification strategies, collaborated with IP and architecture teams to establish project milestones. • Spearheaded test plan reviews for Power Management, Data Path, and Reset functionality of server SoCs. • Design Verification Lead for AMD's multi-chiplet module (CPU + Graphics). • Directed Emulation teams to accelerate boot code validation, reducing turnaround time. • Coordinated Platform Emulation and Firmware validation before tape-out. • Enabled ATE teams to achieve first-time-right silicon patterns, significantly cutting tester costs. • Key debug expert for functional and CReST silicon issues in AMD Server SoCs. • Published two technical papers at AATC (2017, 2022); one selected as a poster. • Mentored engineers, fostering career growth and technical excellence. • Innovated verification methodologies to streamline development cycles. • Collaborated globally to reduce verification complexity without compromising functionality.
Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on Power Management and Design Verification.
Experience: 21 yrs 4 mos
Skills
- Power Management
- Design Verification
Career Highlights
- Expert in Power Management for chiplet-based SoCs.
- Led verification signoff for robust silicon bring-up.
- Published technical papers at AATC.
Work Experience
AMD
Principal Member Of Technical Staff (3 yrs 10 mos)
Senior Member Of Technical Staff (12 yrs 5 mos)
Integrated Device Technology Inc
Design Engineer (6 yrs)
Education
Master of Science - MS at University of Westminster