Mayank Parasrampuria

Software Engineer

Bengaluru, Karnataka, India13 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT methodologies for SoCs.
Led architecture for Google's first mobile SoC.
Strong background in semiconductor testing and design.

Stackforce AI infers this person is a Semiconductor DFT Architect with extensive experience in testing methodologies.

Contact

Skills

Core Skills

Logic DesignDft MethodologyAtpg

Other Skills

ARMASICAlgorithmsApplication-Specific Integrated Circuits (ASIC)Automatic Test Pattern Generation (ATPG)BISTCC++CMOSCore JavaDFTDFT ArchitectureDebuggingDigital ElectronicsEDA

About

Design For Testability

Experience

Google

4 roles

Full Chip DFT & Logic Design Engineer

Nov 2025 – Present · 4 mos

SoC DFT Lead & Architecture
RTL/IP Design

Logic Design

Silicon DFT Engineering Manager III

Oct 2023 – Nov 2025 · 2 yrs 1 mo

DFT Lead and Architect in Next Generation Mobile SoC
Driving Memory Test Methodology for Pixel
DFT Architect

Silicon DFT Engineering Manager II

Promoted

Jul 2022 – Oct 2023 · 1 yr 3 mos

DFT Lead and Architect in Next Generation Mobile SoC
SoC Memory Test Architect & Methodology Lead

DFT Lead

Apr 2019 – Jul 2022 · 3 yrs 3 mos

Led Memory Test Architecture, Methodology & Flow in Google's First Mobile SoC - Tensor
DFT Methodology & Architecture

Nvidia

Senior DFT Engineer

Nov 2015 – Apr 2019 · 3 yrs 5 mos · Greater Bengaluru Area

DFT Methodology & Application Engineering:
> ATPG / Scan Insertion / DFT Architecture / In-System Test / Silicon Bring-up

IEEE standardsProblem SolvingHardware TestingDFT Methodology

Freescale semiconductor

Senior Automotive DFT Design Engineer

Jun 2012 – Nov 2015 · 3 yrs 5 mos · Noida, Uttar Pradesh, India

ATPG - Pattern generation, coverage improvement, vector simulation, pattern delivery to test team.
MBIST - Development, insertion, verification and bring-up (Synopsy SMS, Tessent Memory BIST, Internal Tools - 28nm/55nm).
DFT Insertion - Scan Insertion
DFT Scan Architecture - Clocking in DFT Modes, Development and improvement of architecture to help achieve test pattern count reduction.
Silicon Debug - Scan & MBIST fails
Boundary Scan - Verification, BSDL generation and silicon bring-up.
STA constraint delivery for test modes, Analog safe stating for test modes, Scripting (Developing & maintaining scripts for varied tasks and static design checks etc..)

IEEE standardsProblem SolvingHardware TestingATPG

Maruti suzuki india limited

Intern

May 2011 – Jul 2011 · 2 mos · Gurgaon

Automation of component transfer and study of PLC systems & sensors used for industrial implementation of low cost automation.

Rajasthan electronics & instruments limited

Intern

Jun 2010 – Jun 2010 · 0 mo · Greater Jaipur Area

I did my training in field of Manufacturing and Designing of Solar Photo Voltaic Product, Manufacturing of EMT (Electronic Milk Testers). We were taught on how to manufacturing solar panels and using it in different fields, varying from generation of electricity to using a solar cell to determining the amount of fat content in a liquid(in our case milk). We also did testing of electric meters currently used in households, and learned about how to detect faults and manufacturing problems in them.