Siddesh H Banakar . — Product Manager
CORE COMPETENCIES : • Working knowledge of Unix/Linux, Sun-Solaris, VI editor and Programming in C, Perl, Tcl, Awk, Sed, Verilog, Makefile/Gnumake flow • Good Knowledge of ASIC flow (RTL to GDSII). • Static Timing Analysis, Floorplan, Placement, CTS, Routing, ECO, Physical verification, Synthesis, DFM, DRC, LVS, Parasitic Extraction, Schematic, Layout and Spice Simulation. • An understanding of top view and cross sectional view of CMOS, Finfet, resistance, capacitance • Fabrication process • Basic understanding of RTL design (Verilog), Verification, EDA Tools : • Fusion Compiler, ICC/ICC-2, Innovus/FE, Magma-Talus 1.2, ICV, Astro, Astro-Rail, • Star-RCXT, DC, PT, PT-SI, Composer Schematic, VirtuosoXL, Caliber • Hercules, VCS, Modelsim, Leda, Formality
Stackforce AI infers this person is a Physical Design Engineer specializing in ASIC and SoC development.
Location: Bengaluru, Karnataka, India
Experience: 21 yrs 1 mo
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expert in Physical Design and Static Timing Analysis.
- Extensive experience with leading ASIC design projects.
- Proficient in multiple EDA tools and scripting languages.
Work Experience
Intel Corporation
SoC Design Engineer - CPU Physical Design Engineer (4 yrs)
Sr. Physical Design Engineer - Consultant via Wipro (2 yrs 1 mo)
Wipro Limited
Lead - Physical Design Engineer (2 yrs 5 mos)
Intel Corporation
Physical Design Lead - consultant via Synapse (1 yr 5 mos)
AMD
Sr. Physical Design Engineer - consultant via Synapse (9 mos)
Synapse Design Inc.
Lead - Physical Design Engineer (2 yrs 8 mos)
MStar Semiconductor
Physical Design Engineer - Consultant via Synapse @ Taiwan (5 mos)
Qualcomm
Physical Design Engineer - Consultant via Concept2Silicon Systems (3 yrs 8 mos)
Physical Design Engineer - Consultant via SmartPlay (8 mos)
Concept2Silicon Systems
Physical Design Engineer - Lead (3 yrs 8 mos)
NVIDIA
Physical Design Engineer - Consultant via SmartPlay (11 mos)
SmartPlay Technologies
ASIC Physical Design Engineer (2 yrs 3 mos)
RV-VLSI Design Center
Physical Design Trainee (1 yr 1 mo)
Student (8 mos)
Acharya Institute of Technology
Student (4 yrs 3 mos)
Education
PG Diploma/Certificate at RV-VLSI Design Center, Bangalore
Certificate at UTTARA Inst. of software training-solutions-allied services, Bangalore
BE at Acharya Inst. of Technology, Bangalore (affiliated to VTU)
Certificate at APTECH
PUC at SJVP PU College, Harihar, Davanagere Dr.
SSLC at MKET LK High School, Harihar, Davangere Dr.
