Pratyush Dwivedi

Software Engineer

Cupertino, California, United States8 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in SoC Design and Verification.
Hands-on experience with UVM and System Verilog.
Strong academic background in Computer Engineering.

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on SoC verification and architecture.

Contact

Skills

Core Skills

Soc DesignVerification

Other Skills

AMBAApplication-Specific Integrated Circuits (ASIC)CCadence VirtuosoClock domain crossingDigital ElectronicsField-Programmable Gate Arrays (FPGA)HSPICEIntegrated Circuit DesignIntegrated Circuits (IC)Logic SynthesisNI MultisimPerlRTL simulationSPICE

About

I am a graduate student in Electrical and Computer Engineering at the University of California, San Diego specializing in Computer Engineering. My focus lies on learning nuances of SoC Design and Architecture and I am seeking the opportunity to work in this domain. I have hands-on experience with UVM based SoC verification, System Verilog and RTL Design. Besides, I am well-acquainted with industrial simulation and debugging tools like VCS, Verdi, DVE.

Experience

Apple

2 roles

Graphics Verification Engineer

Jun 2021 – Present · 4 yrs 9 mos · United States

Design Verification Intern

Jun 2020 – Sep 2020 · 3 mos

University of california san diego

Graduate Teaching Assistant

Jan 2020 – Mar 2021 · 1 yr 2 mos · Greater San Diego Area

Graduate Teaching Assistant for:
CSE 141: Introduction to Computer Architecture (Jan-Mar)
CSE 140L: Digital Systems Laboratory (Apr-Jun)
CSE 141L: Project in Computer Architecture (Sept-Present)

Nxp semiconductors

2 roles

Design Engineer, Digital Networking

Jul 2017 – Aug 2019 · 2 yrs 1 mo · Noida Area, India

● 𝐔𝐕𝐌 𝐛𝐚𝐬𝐞𝐝 𝐭𝐞𝐬𝐭𝐛𝐞𝐧𝐜𝐡 𝐞𝐧𝐯𝐢𝐫𝐨𝐧𝐦𝐞𝐧𝐭 𝐝𝐞𝐯𝐞𝐥𝐨𝐩𝐦𝐞𝐧𝐭: Worked over the development of UVM testbench components such as tests environment, agent and soc configuration components for verification of SoC both in RTL and Gate-level simulations.
● 𝐒𝐨𝐂 𝐑𝐞𝐬𝐞𝐭 𝐒𝐭𝐚𝐭𝐞 𝐌𝐚𝐜𝐡𝐢𝐧𝐞 𝐯𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧: Handled the verification of the power-on reset state machine of SoC. It involved developing configuration sequences for soc configuration in the reset phase and testbench scheduling with the SoC's reset phase.
● 𝐂𝐨𝐧𝐬𝐭𝐫𝐚𝐢𝐧𝐞𝐝 𝐫𝐚𝐧𝐝𝐨𝐦𝐬 𝐯𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐞𝐧𝐯𝐢𝐫𝐨𝐧𝐦𝐞𝐧𝐭 𝐝𝐞𝐯𝐞𝐥𝐨𝐩𝐦𝐞𝐧𝐭: It mainly involved integrating AMBA and other internal protocols drivers and monitors for connectivity verification of basic paths to ram, rom and various IP registers, NOC functioning verification and achieving coverage.

UVMSoC verificationRTL simulationAMBAtestbench developmentSoC Design+1

Student Technical Intern

Jan 2017 – Jun 2017 · 5 mos · Noida Area, India

● 𝐑𝐞𝐦𝐨𝐯𝐢𝐧𝐠 𝐗-𝐩𝐫𝐨𝐩𝐚𝐠𝐚𝐭𝐢𝐨𝐧 𝐢𝐧 𝐆𝐚𝐭𝐞 𝐥𝐞𝐯𝐞𝐥 𝐬𝐢𝐦𝐮𝐥𝐚𝐭𝐢𝐨𝐧: Developed an SoC scenario-based flow for disabling timing checks on synchronized flops at the time of simulation to avoid X-propagation in gate-level simulations.
● 𝐕𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐨𝐟 𝐒𝐨𝐂 𝐥𝐨𝐰 𝐩𝐨𝐰𝐞𝐫 𝐦𝐨𝐝𝐞𝐬: Developed a UPF file for low power simulation which involved specifying SoC's power domains, mapping power supplies, isolation and retention cells.
● 𝐏𝐢𝐧-𝐦𝐮𝐱 𝐟𝐥𝐨𝐰 𝐝𝐞𝐯𝐞𝐥𝐨𝐩𝐦𝐞𝐧𝐭 𝐢𝐧 𝐭𝐞𝐬𝐭𝐛𝐞𝐧𝐜𝐡: Developed a flow in testbench to take care of pin muxing in the SoC design in order to ensure correct data flow across SoC and bench.