srikiran gadde

Software Engineer

Bengaluru, Karnataka, India6 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in DFT Compiler and ASIC Flow.
  • Proficient in Verilog and VHDL for design verification.
  • Strong foundation in SCAN Design and ATPG methodologies.
Stackforce AI infers this person is a DFT and ASIC design specialist in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Dft CompilerVerilogAsic FlowDft Fundamentals

Other Skills

ATPG CoverageATPG FaultsATPG for Stuck-at and Transition fault modelsBoundary ScanCadence EncounterCadence VirtuosoFault modelsJTAGPattern simulationsPrimetimeSCAN DRCSCAN DesignSCAN InsertionScan CompressionTCL

Experience

6 yrs 7 mos
Total Experience
3 yrs 3 mos
Average Tenure
6 yrs 3 mos
Current Experience

Mediatek

2 roles

Senior DFT Engineer

Promoted

Feb 2020 – Present · 6 yrs 3 mos

DFT CompilerTetramaxdftvcsVerilogVHDLCadence Virtuoso+3

DFT Engineer

Jun 2018 – Jan 2020 · 1 yr 7 mos

DFT CompilerTetramaxdftvcsVerilogVHDLCadence Virtuoso+3

Chipedge technologies pvt ltd

Trainee

Jan 2018 – May 2018 · 4 mos · Bengaluru Area, India

  • ASIC Flow, DFT fundamentals, SCAN Design, SCAN DRC, SCAN Insertion, Scan Compression, Boundary Scan, JTAG, ATPG Faults, Fault models, ATPG Coverage, ATPG for Stuck-at and Transition fault models and Pattern simulations.
ASIC FlowDFT fundamentalsSCAN DesignSCAN DRCSCAN InsertionScan Compression+7

Education

Lovely Professional University

Bachelor of Technology - BTech

Jan 2011 – Jan 2015

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