Abhinav Loka — Software Engineer
Area of Interest - FPGA RTL Design, IP/block Verification,Soc verification
Stackforce AI infers this person is a skilled FPGA and ASIC verification engineer with a focus on RTL design.
Location: Armoor, Telangana, India
Experience: 3 yrs 7 mos
Skills
- Functional Verification
- Rtl Design
Career Highlights
- Expert in FPGA RTL Design and Verification.
- Proficient in Verilog and SystemVerilog.
- Strong background in Functional Verification methodologies.
Work Experience
Imagination Technologies
Senior Design Verification Engineer (2 mos)
QI-Cap
Design Engineer (3 yrs 5 mos)
Intern (5 mos)
Maven Silicon
RTL Design and Verification Trainee (10 mos)
Education
Integrated dual degree in B.Tech(ECE) and MBA(Marketing) at JNTUH College of Engineering Hyderabad
MPC at Narayana Junior College ,Hyderabad
at Vijay High school,Armoor
at Blue birds model high school, Armoor
