Poonam Nalawade — Software Engineer
4.3 experience(Design + Verification ) in vlsi VLSI Domain Skills : UVM, System Verilog Created verification environment in SV/UVM, Verilog from scratch Packet Generator in C+UVM Environment,Simulation, Debugging Verilog, VHDL Verification methodology Constraint Random verification Bus Protocol PCIe gen2/gen3/gen4/gen5/gen6,AHB-APB Bridge,UART EDA Tool Verdi, simvision Questasim,Xilinx ISE,Vivado,Active HDL,Synopsys - VCS,Cadence - NCsim, TannerEDA-MentorGraphics Knowledge Digital Design concepts,RTL coding, Simulation, Synthesis Platforms Linux, Windows FPGA Board Spartan6, Zynq(Zybo) Worked on SOC/IP verification Scripting Language Shell, PERL Basics, Makefile Understanding of code coverage and functional coverage
Stackforce AI infers this person is a VLSI Verification Engineer with expertise in semiconductor design and verification.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 6 mos
Skills
- Verification
- Uvm
- Subsystem Verification
- Block Level Verification
- Ip/soc Verification
- Vlsi Design
Career Highlights
- Expert in VLSI design and verification methodologies.
- Proficient in UVM and System Verilog for complex projects.
- Strong leadership in managing verification teams and projects.
Work Experience
Logic Fruit Technologies
Senior Verification Engineer II (3 yrs 7 mos)
Senior Verifcation Engineer (9 mos)
R&D Engineer in Verification Department (1 yr)
PerfectVIPs
Asic Verification Engineer (1 yr 3 mos)
Jeet Techno Solutions LLP
VLSI Design Engineer (5 mos)
TechnoLexis
VLSI Design Engineer (6 mos)
Education
Bachelor of Engineering - BE at KBP College of Engineering, Satara Shivaji University
Master of Science - MS at Manipal Academy of Higher Education, Manipal
