Hemanth Chintalapudi

DevOps Engineer

Bengaluru, Karnataka, India5 yrs 10 mos experience

Key Highlights

4+ years of experience in ASIC design.
Passionate about making VLSI education accessible.
Keynote speaker inspiring future engineers.

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on VLSI education and creative communication.

Contact

Skills

Core Skills

Rtl DesignDigital Electronics

Other Skills

Verilog HDLPCIeEthernetComputer ArchitectureFront-End DesignMicrosoft PowerPointInternet of Things (IoT)basics of plcbasics of pythonbasics of matlab onrampsimulinkDigital DesignsSystemVerilog

About

Hey there! 👋 I’m an ASIC Design Engineer by day, Silicon Sketch Artist by passion! 🎨 With 4+ years in the semiconductor world, I specialize in making complex chip design concepts click through simple, creative visuals. Whether it’s drawing diagrams or breaking down VLSI magic, I’m all about turning tough topics into easy-to-grasp ideas. 💡 When I’m not designing silicon, I’m spreading the love for tech as a content creator, teacher, and keynote speaker. I’ve had the awesome opportunity to speak at four engineering colleges (till date), inspiring the next generation of innovators to dive deep into the world of semiconductors. My mission is to provide quality VLSI education and make learning fun and accessible for all. Let’s connect if you're passionate about VLSI, education, and making engineering a bit more fun and accessible! For collaborations, feel free to reach me at: chintalapudihemanth.official@gmail.com. Thank you!

Experience

Cadence

Lead Design Engineer

Sep 2025 – Present · 6 mos · Bengaluru, Karnataka, India · On-site

7rays semiconductors india private limited

Senior Design Engineer - ASIC

Jun 2024 – Aug 2025 · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

Logic fruit technologies

2 roles

RTL Design Engineer

Promoted

Dec 2021 – Jun 2024 · 2 yrs 6 mos

Experienced RTL Design Engineer, Implemented Precision Time Protocol IP from
scratch. I have been responsible for designing and implementing PTP IP logic, testing and
debugging.
Conducted debugging on hardware and in simulation, identifying and resolving issues
related to timing, synchronization, and signal integrity.
Collaborated with cross-functional teams, including software developers and hardware
engineers, to develop and test new features and improve system performance.
Created and maintained design documentation, including specifications, design
documents, and test plans, to ensure compliance with design requirements and facilitate
knowledge transfer.

Verilog HDLDigital ElectronicsRTL Design

RTL Design Engineer

Dec 2021 – Apr 2022 · 4 mos

Tessolve

Post Silicon Validation - Test Engineer - 1

Jan 2020 – Sep 2021 · 1 yr 8 mos · Bengaluru, Karnataka, India

Skill set learned as I worked as a post-silicon validation Engineer.
Developed Test flows for different test cases for all IPs like Phase Locked Loop(PLL), Linear Drop-out Voltage Regulator(LDO), and DLL.
Hands-on experience with Advantest V93K System On-Chip(SOC) platforms.
Developed production and characterization test programs and executed test solutions.
Experience with source repository systems - GIT.
Worked on test enhancement and test-time reduction activities.
Familiar with statistical data analysis tools like Exensio and Optimal plus.
Sound understanding of program development including the study of specifications, requirements, integration, testing, documentation, and support.