Vikas Kumar — Product Engineer
Currently immersed in the world of R&D as a Verification Engineer at Logic Fruit Technologies, I'm leveraging my academic background in Electronics and Communication from IIIT Ranchi to drive innovation in verification processes. My expertise in UVM, SystemVerilog plays a pivotal role in ensuring the integrity and reliability of electronic components and systems.
Stackforce AI infers this person is a Verification Engineer with a focus on Electronics and Communication in R&D.
Location: Sikar, Rajasthan, India
Experience: 3 yrs
Skills
- Universal Verification Methodology (uvm)
- System Verilog
Career Highlights
- Expertise in UVM and SystemVerilog for verification processes.
- Strong academic background in Electronics and Communication.
- Hands-on experience in power electronic device simulation.
Work Experience
Logic Fruit Technologies
R&D Verification Engineer (1 yr 4 mos)
R&D Verification Engineer Trainee (4 mos)
Verification Intern (2 mos)
Defence Research and Development Laboratory (DRDL) - DRDO
Research internship (2 mos)
House of Geeks Technical Society of IIIT Ranchi
Head of Community (11 mos)
Community Coordinator (5 mos)
Education
Bachelor of Technology - BTech at Indian Institute of Information Technology Ranchi
