Parthasarathy Ramesh

CEO

Bengaluru, Karnataka, India10 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in Digital Design Verification at Texas Instruments
Strong background in System on a Chip (SoC) technologies
Proven leadership in managing technical teams and projects

Stackforce AI infers this person is a Digital Design Verification Engineer with expertise in semiconductor and electronics industries.

Contact

Skills

Core Skills

System On A Chip (soc)Formal VerificationUniversal Verification Methodology (uvm)

Other Skills

Unified Power Format (UPF)ARM Cortex-MARM ArchitectureSystemVerilogFunctional VerificationEvent ManagementEvent PlanningCC++Microsoft OfficePhotoshopVerilogCustomer ServiceTeamworkTeam Leadership

About

I am Parthasarathy Ramesh currently working for Texas Instruments India as a Digital Design Verification Engineer. I graduated with a B.Tech(Honours) from National Institute of Technology, Tiruchirappalli in Electronics and Communication Engineering in May 2018. Contact me at : rsp131196@gmail.com

Experience

Texas instruments

5 roles

Member Group Technical Staff

Nov 2024 – Present · 1 yr 4 mos

Digital Design Manager

Sep 2023 – Present · 2 yrs 6 mos

Design Verification Lead

Promoted

Feb 2023 – Present · 3 yrs 1 mo

Senior Design Verification Engineer

Feb 2021 – Jan 2023 · 1 yr 11 mos

Unified Power Format (UPF)Formal VerificationSystem on a Chip (SoC)ARM Cortex-MARM Architecture

Digital Engineer

Jun 2018 – Jan 2021 · 2 yrs 7 mos

Universal Verification Methodology (UVM)Formal VerificationSystem on a Chip (SoC)

Samsung semiconductor

Summer Internship

May 2017 – Jul 2017 · 2 mos · Bangalore

Pragyan - nit trichy's technical fest

3 roles

Head Of Quality Assurance

Promoted

Apr 2017 – Apr 2018 · 1 yr

Headed a team of 38 organisers apart from helping in taking decisions related to Pragyan as a part of the Pragyan Core Committee.
Responsible for overlooking and helping with the documentation of ISO 9001:2015 and ISO 20121:2012 certifications and helping conduct the techno-managerial fest smoothly.
Responsible for the patronages from UNESCO, CEE/SAYEN, Ministry of Electronics and Information Technology and Make in India which Pragyan has.
Responsible for conducting internal audits and for being a part of external audit during Pragyan.
Instrumental in helping the trademark Pragyan, NIT Trichy achieve Registered status.
Instrumental in Registering the Pragyan, NIT Trichy Trademark

Quality Assurance Manager

Jul 2016 – Apr 2017 · 9 mos

Responsible for taking care of events and maintaining records for audits which are essential for the ISO 9001 and ISO 20121 certifications which Pragyan has.
Responsible for collecting, analysing and maintaining customer feedback for that edition of Pragyan and the editions to come.
Responsible for maintaining documents for ISO 9001:2015 and managing 20 coordinators who took care of 35+ events.

Event Manager, Quality Assurance Coordinator

Aug 2015 – Jul 2016 · 11 mos

Responsibilities as an Event Manager:
Managing events
Writing event reports
Responsibilities as a Quality Assurance Coordinator:
Maintaining documents of events happening in Pragyan which are directly helpful for the audits.
Overlooking assigned events and help organise them.
Collecting feedback from participants and analysing them.

Doordarshan kendra , chennai

Industrial Trainee

Dec 2015 – Dec 2015 · 0 mo · Chennai Area, India

Doordarshan is India's Central Government founded public service broadcaster, a division of Prasar Bharati. It is one of India's largest broadcasting organisations and is also India's most watched TV channel. Doordarshan Kendra , Chennai is one of the oldest Kendras in the country having been setup in the mid 1970s. The industrial training provided a varied exposure about the theory and technicalities in the fields of mass communication , especially pertaining to Television broadcasting , satellite communication and Digital Satellite News Gathering.