Gaurav Raj

Software Engineer

Bengaluru, Karnataka, India3 yrs 8 mos experience

Key Highlights

Expert in Design Technology Co-Optimization for advanced process nodes.
Proven track record in PPA optimization and Device Integration.
Strong collaboration skills bridging Design and Process teams.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Technology Development.

Contact

gauravr363@gmail.com LinkedIn

Skills

Core Skills

Design Technology Co-optimizationDevice And Process IntegrationPhysical Design FlowPhysical Verification

Other Skills

PPA optimizationDesign EnablementDTCOPower and Performance ModelingPost-Silicon ValidationStandard-Cell Architecture OptimizationFull-Chip Physical Design FlowFloorplanningPower PlanningPlace & RouteTiming ClosureAutomation and scriptingCustom IP integrationRedhawkICC

About

Self-motivated and Detail-Oriented Design Engineer at Qualcomm, specializing in Design-Technology Co-Optimization (DTCO) to drive innovation across advanced process nodes. Proven expertise in Device and Process Integration, Design Enablement, and Technology Development for High-Performance, Scalable SOCs. Strong foundation in Semiconductor Physics, Yield Enhancement, and PPA (Power, Performance, Area) optimization. Adept at bridging Design and Process teams to align Technology capabilities with Product Goals, enabling efficient and robust Silicon solutions.

Experience

Qualcomm

Senior Physical Design Engineer

Mar 2025 – Present · 1 yr · Bengaluru, Karnataka, India

Defining and Tracking PPA Goals across Design Cycles.
Collaborating with Architecture, RTL, and Physical Design teams to drive efficient implementation.
Driving DTCO (Design Technology Co-Optimization) initiatives with Foundry and EDA Partners.
Performing Block-Level Physical Design Regressions to validate PPA Boosters.
Performing workload-based Power and Performance Modeling.
Supporting Post-Silicon Validation and correlation with Pre-Silicon Models.
Evaluating and Optimizing Standard-Cell Architectures for PPA improvements.
Exploring 3DIC and STCO (System Technology Co-Optimization) strategies for Next-Gen Designs.

PPA optimizationDevice and Process IntegrationDesign EnablementDTCOPower and Performance ModelingPost-Silicon Validation+2

Amd

Physical Design Engineer

Jul 2022 – Feb 2025 · 2 yrs 7 mos · Hyderabad, Telangana, India

Full-Chip Physical Design Flow: Floorplanning, Power Planning, Place & Route, CTS, Timing Closure.
Physical verification: DRC, LVS, IR Drop, EM Analysis.
Integration of custom IPs: RAMs, PLLs, high-speed IOs.
Automation and scripting: Python, Tcl, Perl, Shell.
Tools: Synopsys ICC2/PT, Cadence Innovus/Tempus, Mentor Calibre.

Full-Chip Physical Design FlowFloorplanningPower PlanningPlace & RouteTiming ClosurePhysical verification+4