Bhanuprakash G V — Software Engineer
Full Chip Timing analysis, Accelerator Physical Design/Timing closure, CPU physical design, Physical design flow automation, static timing methodology. Handled sign-off timing closure of large SOC, which are designed for AI/ML HPC computing in latest fab technologies. Physical design Tech lead for ATOM CPU designed for leading edge Intel foundry technology, driving aggressive power performance goals, design closure on timing, EMIR, physical verification. Timing integration/closure of multiple functional blocks of ATOM CPU. Physical Design and timing closure of ARM CPU's in 7nm/10nm/14nm/20nm/28nm at QUALCOMM Static timing analysis of A76/A73/A57/A53 based ARM CPU sub-system. Place & Route, Timing closure of L3 cache in 7ff technology. Timing closure of A73/A72/A57 CPU sub-system for 2+GHz. Lead Timing closure of power efficient cores for Qualcomm kryo CPU's. Physical Implementation of A57 bus for 2GHz frequency. Leading 28nm GPU implementation and timing analysis of 65/45/28nm complex SOC's. * Timing closure of quad-core A7 for 28nm chip. * Technical lead and STA for A320 graphics quad core for MSM 8960 Pro * Timing Closure of A5 sub system for 45nm chip Development of STA flows * Automation of Timing ECO methodologies. * In-house ECO flow Automation at Qualcomm Specialties: Synthesis, Place and Route, Static Timing Analysis/Timing closure , Low Power optimization Strategies/Methodologies.
Stackforce AI infers this person is a Physical Design Engineer specializing in SOCs for AI/ML applications.
Location: Austin, Texas, United States
Experience: 22 yrs 2 mos
Skills
- Static Timing Analysis
- Physical Design
- Soc Design
- Timing Closure
- Timing Analysis
Career Highlights
- Led timing closure for advanced AI/ML SOCs.
- Expert in physical design for ARM and Intel CPUs.
- Pioneered automation of timing ECO methodologies.
Work Experience
Meta
Silicon Engineer (4 mos)
Rivos Inc.
Data Parallel Accelerator Timing Lead / Physical Design (2 yrs 9 mos)
SambaNova Systems
Principal Engineer (1 yr 10 mos)
Intel Corporation
Engineer (3 yrs)
Qualcomm
Senior Staff Engineer (2 yrs)
Staff Engineer (3 yrs)
Lead, Sr Engineer (2 yrs 11 mos)
Senior Engineer (2 yrs 5 mos)
Engineer (3 yrs 11 mos)
Education
M S at Birla Institute of Technology and Science, Pilani
Bachelor of Engineering at Visvesvaraya Technological University
at Government First Grade College, Behind BEO Office, Robertsonpet, 3rd Cross, KGF-563 122, Kolar Dist.
school at Taylor high school -Andhra Pradesh ,India
