Pallavi Deshmukh

Software Engineer

Bengaluru, Karnataka, India10 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ASIC design and VLSI implementation.
  • Proficient in scripting with PERL and TCL.
  • Strong background in frontend ASIC design automation.
Stackforce AI infers this person is a VLSI and ASIC design engineer with strong automation skills.

Contact

LinkedIn

Skills

Core Skills

AsicVlsiPhysical Design

Other Skills

Verilog HDLCadence®ModelSimStatic Timing AnalysisSynthesisLECERCtiming closureRTL Quality AnalysisFrontend ASIC Design AutomationPlacementRoutingPERLTCLC Language basics

About

Ownership of Subsys level Pre-Layout implementation (Synthesis, timing closure and netlist quality checks) and Post-STA. Involved in Frontend ASIC Design Automation Coding skills in PERL, TCl, Verilog Trained in Synthesis-GDSII Familiar with Physical Design Flow Hold Master's degree in VLSI from VIT University, India.

Experience

10 yrs 11 mos
Total Experience
3 yrs 7 mos
Average Tenure
8 yrs 8 mos
Current Experience

Mediatek

2 roles

Senior Engineer

Promoted

Jun 2018 – Present · 7 yrs 10 mos

Verilog HDLCadence®ModelSimStatic Timing AnalysisVLSIASIC

Engineer

Aug 2017 – Jun 2018 · 10 mos

  • Responsible for Subsys level prelayout implementation (Synthesis, LEC, ERC, timing closure) for Smartphone and Application specific SOC
SynthesisLECERCtiming closureASICVLSI

Qualcomm

Consultant

Jul 2015 – Jul 2017 · 2 yrs · bangalore

  • CAD Engineer : Frontend flows - RTL Quality Analysis
  • Involved in Frontend ASIC Design Automation
RTL Quality AnalysisFrontend ASIC Design AutomationASICVLSI

Smartplay technologies - an aricent company

Intern (Physical Design)

Mar 2015 – Jun 2015 · 3 mos · Bengaluru Area, India

  • Trained in Synthesis and Physical Design
  • Worked on Synthesis, Placement - Routing of design block.
  • Understanding of Constraints on the design from Synthesis level to the backend
  • Developed scripting in PERL and TCL.
  • Timing Analysis at block level.
  • Tools used: Synopsis Design Compiler, ICC, Prime Time
SynthesisPlacementRoutingPERLTCLPhysical Design+1

Education

VIT University, Vellore

Master of Technology (M.Tech.) — VLSI Design

Jan 2012 – Jan 2014

G.H. Raisoni College of Engineering, Nagpur

Bachelor of Engineering (B.E.) — Electronics and Telecommunication

Jan 2008 – Jan 2012

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