Ujjwal Prakash

Software Engineer

Bengaluru, Karnataka, India14 yrs 2 mos experience
Highly Stable

Key Highlights

  • Expert in VLSI and ASIC design methodologies.
  • Strong background in physical design and netlist implementation.
  • Proficient in scripting with Tcl and Perl for automation.
Stackforce AI infers this person is a VLSI and ASIC design expert with strong physical design capabilities.

Contact

LinkedIn

Skills

Core Skills

VlsiAsicPhysical DesignNetlist To Gds Implementation

Other Skills

DRCTimingLVSCadenceTCLPerlICCEncounterCalibre

Experience

14 yrs 2 mos
Total Experience
5 yrs 2 mos
Average Tenure
10 mos
Current Experience

Mediatek

Senior Staff Engineer

Jun 2025 – Present · 10 mos · Bengaluru, Karnataka, India

DRCTimingVLSIASICLVSCadence+1

Qualcomm

4 roles

Staff Engineer

Nov 2021 – May 2025 · 3 yrs 6 mos

Sr. Lead Engineer

Nov 2017 – Nov 2021 · 4 yrs

Senior Engineer

Promoted

Apr 2016 – Oct 2017 · 1 yr 6 mos

Engineer

Sep 2014 – Mar 2016 · 1 yr 6 mos

  • I am a part of the graphics team.

Amd

Consultant

Jan 2012 – Apr 2014 · 2 yrs 3 mos · Hyderabad Area, India

  • Responsible for netlist to gds implementation. Fixing timing issues and drc's and lvs' issues.
  • Worked on 28nm and 20nm technology. Worked on ICC, Encounter, Pt, Calibre. Good at tcl & perl scripting
TimingDRCLVSICCEncounterCalibre+3

Einfochips

Physical Design Engineer

Oct 2011 – Aug 2014 · 2 yrs 10 mos

  • I am responsible for nelist to gds implementation of block/tiles. I am responsible for complete PnR flow. Good knowledge on Synopsys ICC, Cadence First Encounter, Pt, Calibre. Good at scripting in Tcl & Perl
CadenceTCLPerlPhysical Design

Education

SPSU ,Udaipur

Bachelor of Technology (B.Tech.)

Jan 2007 – Jan 2011

Baldwin Academy ,Patna

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