Prateek Singhal — Software Engineer

Graduate with Master’s Degree in VLSI Engineering with over 2 year background in VLSI Industry with exceptional teamwork and communication skills. Excellent reputation for resolving problems and meeting deliverables Worked on Tech node ranging from 5nm, 4nm and 3nm Responsible for handling critical layout and converged it finding all the issues at the earliest and delivered the block ahead of schedule. PROFILE • ABOUT ME WORK EXPERIENCE Worked using Fusion Compiler, Innovus, IC Validator Vue and Calibre Tools Handled critical sections which had multiple LVS issues, ERC and SOFTCHECK Had closely work with section owners. Worked on SOC Analysis and provided indept review with respect to partition level Fixes Handled multiple partitions for layout erification process. plemented ECOs (Functional & Timing) manually ith minimum pact of DRCs in highly congested area. esponsible for closing the Pre base-fill, Base-fill and Metal-Fill Violations in all Layout verification aspects such as DRC, LVS, Antenna and Density.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Verification and layout optimization.

Location: Noida, Uttar Pradesh, India

Experience: 3 yrs 11 mos