Chirag Singhal

Product Engineer

Konch, Uttar Pradesh, India2 yrs 6 mos experience

Highly Stable

Key Highlights

Expert in CDC and RDC checks for multi-million gate IP.
Proficient in Unified Power Format for low power design verification.
Hands-on experience with industry-standard verification tools.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in low power design and verification.

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Skills

Core Skills

Unified Power Format (upf)Assertion Based Cdc Verification

Other Skills

LEC cadence conformalFusion compilerVC Formal Low PowerApplication-Specific Integrated Circuits (ASIC)Python scriptingPCIeETHERNET PHYGPIORTL CodingPerlComputer ArchitectureDigital DesignsSpyglass CDC & RDC checks and Lint ChecksUPF Power aware Design and VerificationDesign for debug

About

• Design Engineer at INTEL • Working on PCIE subsytem • Worked on GPIO subsystem, Ethernet • Hands on Verilog, System Verilog and System Verilog Assertions • Good understanding of Clock Domain and Reset Domain Crossing Issues. • Hands on CDC & RDC checks & Lint checks (with Vc-Spyglass & vc-lint) on Multi-million gate IP • Hands on Assertions based Verification of CDC & RDC • Hands on Design of Debug (DFX) to provide observability and controllability during Post-Silicon Val. • Good understanding of Low Power design Verification & UPF • Familiarity with UNIX, Python scripting, OOP concepts

Experience

2 yrs 6 mos

Total Experience

2 yrs 6 mos

Average Tenure

2 yrs 6 mos

Current Experience

Intel corporation

SoC Logic Design Engineer

Nov 2023 – Present · 2 yrs 6 mos · Bengaluru, Karnataka, India · On-site

LEC cadence conformalFusion compiler

Synopsys inc

R&D Engineer (contract)

Jul 2023 – Oct 2023 · 3 mos · Bengaluru, Karnataka, India · Hybrid

1. Converted VCLP Test cases to VC Formal Low power Test cases using Tcl.
2. Modified and Written UPF for various block level RTL.
3. Performed Power aware connectivity checks and Formal LP Property Checks at block level using VC Formal.

Unified Power Format (UPF)VC Formal Low Power

Intel corporation

Intern

Jul 2022 – Jun 2023 · 11 mos · Bengaluru, Karnataka, India · Hybrid

Performed CDC & RDC and Lint Checks for multi-million gate IP.
Analyzed & suggested fix for various Complex design problem related to CDC & RDC.
Worked on Design for debug (DFX) for identifying Debug signals in IP.
Inserted Debug Signals in Intel's DFX debug framework by developing Python script to enhance efficiency improvement for observability and controllability during Post Silicon Val.
Validated debug structure inserted for connectivity and security in Verdi.
Worked on Assertion based verification of CDC & RDC
Hands on with industry standard tools like Spyglass, Verdi, VCLP

Assertion based CDC VerificationApplication-Specific Integrated Circuits (ASIC)