Jan 2016 – May 2016 · 4 mos · Cupertino, california

Aug 2015 – Dec 2015 · 4 mos

May 2015 – Aug 2015 · 3 mos · Santa Clara

• Developed 10nm placement and routing flow.
• Carried out experiments to bring down the DRCs.
• Carried out floorplan scaling trials for optimal perfomance in terms of area,speed and power.
• Interfaced with Synopsys to drive tool fixes & improvements in support of on-going activities on 10nm.
• Interfaced with Standard Cell Library team to drive cell fixes for DRCs.
• TOOLS:
• Synopsys ICC/ICC2 : Floorplanning,Placement,CTS,Routing

Jun 2012 – Jun 2014 · 2 yrs · Noida Area, India

• Carried out Synthesis through GDSII preparation including scan stitching, floorplanning, placement, clock tree synthesis,routing, signal integrity check, DFM & DRC.
• Implemented Power shut off technique using power switch insertion to reduce the deep sleep mode power of the SoC.
• Checked Logic equivalence between RTL and netlist, Coded CPF for low power intent & validated the power intent with CLP.
• Designed constraints for both functional & scan mode.
• Analyzed Block level timing both flattened and with ETM flow.
• Timing aware floating metal ll insertion in Encounter.
• Created flow for noise analysis in AAE-SI & analyzed the dierences in timing between AAE-SI & Celtic as noise engines.
• Compared NLDM and ECSM models for timing for logic cells.
• Performed manual ECO as well as Conformal ECO patch flow for post mask ECO Rev.
• Ran Spice simulation for failing timing paths in Spectre and comparison with EDA tool modeled timing.
• Interfaced with tool vendors to drive tool fixes and improvements in support of on-going and planned CAD activities.
• Interface with the design team to drive design modifications to resolve congestion and timing issues.
• TOOLS:
• Cadence SoC Encounter : Floorplanning,Placement,CTS,Routing,DFM,Timing Optimization
• Cadence ETS : Static Timing Analysis, SI/Noise analysis(Celtic/ETS-SI)
• Cadence RTL Compiler : Synthesis
• Cadence Conformal : LEC, CLP, Pre mask & post mask ECO
• Cadence QRC : Parasitic extraction
• Mentor Calibre : Signo LVS & DRC checks at block level
• Cadence Spectre : Spice simulation
• Cadence Virtuoso : Schematics & Layout design
• Mentor ModelSim : RTL simulation