Animesh Pandey

Software Engineer

Noida, Uttar Pradesh, India10 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ASIC design and Static Timing Analysis.
  • Proven track record at Qualcomm and NVIDIA.
  • Strong background in digital design methodologies.
Stackforce AI infers this person is a highly skilled ASIC engineer specializing in digital design and timing analysis in the computer hardware industry.

Contact

LinkedIn

Skills

Core Skills

AsicStatic Timing Analysis

Other Skills

RTL DesignCDCPLDRCPIEUPFRTL PowerPTPXCLPFVConformal-ECODFTOCC insertionSynthCMSTiming Constraints

About

Experienced Senior Application Specific Integrated Circuit Engineer with a demonstrated history of working in the computer hardware industry. Strong engineering professional with a Bachelor of Technology (BTech) focused in Electronics and Communications Engineering from Delhi College of Engineering.

Experience

10 yrs 8 mos
Total Experience
5 yrs 4 mos
Average Tenure
6 yrs 10 mos
Current Experience

Qualcomm

Staff Engineer

Jun 2019 – Present · 6 yrs 10 mos · Noida, Uttar Pradesh, India

  • SerDes PHY Digital design :-
  • RTL Design
  • CDC, PLDRC
  • PIE, UPF, RTL Power (PowerArtist), PTPX
  • CLP, FV, Conformal-ECO
  • DFT - OCC insertion (Tessent)
  • Synth, CMS (Timing Constraints), Fishtail, STA
RTL DesignCDCPLDRCPIEUPFRTL Power+13

Nvidia

Sr. ASIC Engineer

Aug 2015 – Jun 2019 · 3 yrs 10 mos · Bengaluru, Karnataka, India

  • STA Methodology/CAD
  • Block/Chiplet level Timing closure.
STA MethodologyCADBlock Timing ClosureChiplet Timing ClosureStatic Timing Analysis

Education

Delhi College of Engineering

Bachelor of Technology (BTech)

Jan 2011 – Jan 2015

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