Ayush Agrawal

Software Engineer

Bengaluru, Karnataka, India4 yrs 3 mos experience
Highly Stable

Key Highlights

  • Senior VLSI Engineer with strong academic background.
  • Experience in RTL design at MediaTek.
  • Proficient in VLSI and Digital Electronics.
Stackforce AI infers this person is a VLSI Engineer with expertise in digital design and embedded systems.

Contact

LinkedIn

Skills

Core Skills

Very-large-scale Integration (vlsi)Digital Electronics

Other Skills

Computer ArchitectureStatic Timing AnalysisVerilogArduinoEngineeringC++CommunicationProgram Development

About

Intern at Mediatek as VLSI RTL Design Engineer

Experience

4 yrs 3 mos
Total Experience
3 yrs 6 mos
Average Tenure
9 mos
Current Experience

Mediatek

2 roles

Senior Engineer - RTL DESIGN

Jul 2025 – Present · 9 mos · Bengaluru, Karnataka, India · On-site

Very-Large-Scale Integration (VLSI)Digital Electronics

RTL Design Intern

Jan 2025 – Jun 2025 · 5 mos · Bengaluru, Karnataka, India · On-site

Acm, association for computing machinery

Member

Nov 2019 – May 2023 · 3 yrs 6 mos · Indore, Madhya Pradesh, India

Education

BITS Pilani, Hyderabad Campus

Master of Engineering - MEng — Embedded systems

Jul 2023 – Jul 2025

Institute of Engineering & Technology DAVV, Indore

Bachelor of Technology - BTech

Jan 2019 – Jan 2023

India International Public School, Dabra Gwalior

Senior Secondary (10+2) — PCM

Jan 2016 – Jan 2018

India International Public School, Dabra Gwalior

Secondary (10)

Jan 2012 – Jan 2016

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