P Prashanth

Product Engineer

Hyderabad, Telangana, India5 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in RTL design and static timing analysis.
  • Proficient in creating design verification environments.
  • Strong experience in managing design projects and teams.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL design and verification.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignStatic Timing Analysis

Other Skills

RTL CodingECOLECFishtailSynchronizersUPFLintRDCCDCQuestaSimPythonTCL scriptingDigital DesignVerilogFPGA

About

working as a RTL Design Engineer

Experience

5 yrs 6 mos
Total Experience
1 yr 10 mos
Average Tenure
3 yrs 2 mos
Current Experience

Amd

Silicon Design Engineer

Apr 2024 – Present · 2 yrs · Hyderabad, Telangana, India · On-site

  • working as a contractor in AMD, worked on NOC,tool regression,cdc,lint rdc,clp,sdcqa,sta,syn,dftdrc,lec,eco,python,tcl scripting
  • created environment setup for lint,cdc,rdc,fishtail,PT,spyglass dftdrc.
  • soc and subsystem level lint checks with spyglass lint.
  • soc and subsystem level CDC checks with Questa CDC and spyglass CDC.
  • soc and subsytem level RDC checks with Questa and Spyglass RDC.
  • Analyzed reported setup and actual design issues and fixed.
  • Take the ownership for the enterie Excite setup.
  • Team management.
  • LEC & ECO runs.
  • Gate cdc and glitch check with Questa cdc and spyglass cdc&rdc.
  • completed assigned tasks on time and met the schedules and milestones.
  • core level RTL and IP integration
RTL CodingECOLECFishtailStatic Timing AnalysisSynchronizers+8

Sion semiconductors private limited

RTL Design Engineer

Feb 2023 – Present · 3 yrs 2 mos · Hyderabad, Telangana, India

  • Developing Designs from scratch strong knowledge on Digital, Verilog and design concepts experiance on lint, CDC, RDC, STA, FPGA
Digital DesignVerilogLintCDCRDCStatic Timing Analysis+2

Neo trend ev systems pvt ltd

Asst. Electronics Engineer

Jan 2019 – Nov 2020 · 1 yr 10 mos · Hyderabad Area, India

Sumedha design systems pvt ltd(jagruthi educational welfare society)

Design Verification Engineer

Jan 2018 – Jul 2018 · 6 mos · Hyderabad, Telangana, India

Education

CMR Technical campus

Bachelor of Technology - BTech

Jan 2014 – Jan 2017

Indur Institute of Engineering & Technology

Diploma

Jan 2011 – Jan 2014

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