Devika R Nair — Product Engineer

Physical Design Engineer experienced in handling RTL to GDSII flow in various technology nodes to meet tape-in design quality. Tasks undertaken include full physical design flow - Reading the design, Floor Planning, Placement, CTS and Routing using Fusion compiler. Verification responsibilities included Star RC extraction, timing fixes(STA) using Prime Time. Also worked in methodologies for improving robustness, power, performance, area and timing for optimizing physical design constraints. Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing physical design related TFM. Partners with physical design, circuits, CAD, RTL, tool/flow owners, and third-party vendor teams to continuously improve physical design methodologies and efficiencies.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in VLSI methodologies.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 8 mos