Atul Pawar

Product Engineer

Pune, Maharashtra, India8 yrs 6 mos experience

Most Likely To Switch

Key Highlights

Expert in DDR memory controller design and verification.
Strong background in low power design implementation.
Proficient in RTL design and synthesis methodologies.

Stackforce AI infers this person is a VLSI design engineer with expertise in memory solutions and low power design.

Contact

atulpaw1993@gmail.com LinkedIn

Skills

Core Skills

Design VerificationStaRtl DesignLow Power DesignDdr-ctrlTechnical SupportDdr Memory ControllerLow Power ImplementationFormal Verification

Other Skills

DDR5LPDDR5HBM3Image and Sensor subsystemMIPI PHYRTL designingRTL Quality checkLow power check designDDR-PHYArea estimationCustomer feedbackCompetitive analysisDevelopmentTest Plan Bring-upDebugging

About

Hi !!! I am Atul P Pawar. Worked at Cadence design Systems, Pune. DDR CTRL support for LPDDR, PCDDR, GDDR and HBM memory solutions. I have expertise in Low power design implementation and low poy checks, Synthesis, UPF in Qualcomm, Bangalore. Worked on DDR-Controller IP designs - RTL to Synthesis, Low power checks of RTL and Netlist, Improving Quality of Results Trained and worked on – 1) Spyglass for RTL linting and CDC. 2) DC/DCT/DCG/Genus for Synthesis : for DDR-CTRL IP synthesis. Sound Knowledge about Synthesis. 3) LEC : FV check between RTL vs modified RTL, RTL vs netlist ,netlist vs optimized netlist. 4) PrimeTime i ) PT Static Timing Analysis : For timing analysis for PD netlist . ii) PTPX power analysis : Power analysis for clk network , sequential , Hard-Macro power . 5) CLP : Unified Power Format for MV-UPF Low power designs and for advanced technology nodes. Good understanding and implementation of UPF/CPF (Power intent file) for low power implementation.

Experience

8 yrs 6 mos

Total Experience

1 yr 8 mos

Average Tenure

2 yrs 11 mos

Current Experience

Confidential

Principal Design Engineer

Jun 2023 – Present · 2 yrs 11 mos · Pune District, Maharashtra, India

Micron technology

Senior Engineer

Nov 2021 – May 2023 · 1 yr 6 mos · Hyderabad, Telangana, India

DDR5, LPDDR5 and HBM3 STA and Design verification.

DDR5LPDDR5HBM3STADesign verification

Samsung electronics

Staff Engineer

May 2021 – Nov 2021 · 6 mos · India

Working in Image and Sensor subsystem team.
MIPI PHY (D-PHY, C-PHY, A-PHY) developer.
Analog + Digital design engineer.
RTL designing and development ;
RTL Quality check : RTL-LINT, CDC, Synth elan check.
Low power check design.

Image and Sensor subsystemMIPI PHYRTL designingRTL Quality checkLow power check designRTL Design+1

Cadence design systems

Lead Product Engineer

Jan 2020 – May 2021 · 1 yr 4 mos · Pune, Maharashtra, India

Working on DDR-CTRL and DDR-PHY IP from CDNS .
Updating DDR R&D teams with the major customer feedback and competitive analysis.
Area estimation on DDR-CTRL for different configuration and different PHY shape and lengths.
Technical support for
LPDDR : LPDDR3, LPDDR4 and LPDDR5
PCDDR : DDR3, DDR4 and DDR4 for UDIMM, RDIMM and LRDIMM
GDDR : GDDR6

DDR-CTRLDDR-PHYTechnical supportArea estimationCustomer feedbackCompetitive analysis

Qualcomm

3 roles

Senior Engineer

Promoted

Nov 2019 – Dec 2019 · 1 mo

Worked on DDR Sub-System Team as IP Design Engineer of DRAM Memory Controller integration team.
I was responsible for RTL Design and Development of DDR memory controller IP for multiple projects. Each project demands a different set of features and delivered on time with good quality RTL.
Owner for DDR Sub-System design and support to design verification team in Test Plan Bring-up, debugging of test scenarios and resolving their queries.
Drives many initiative in 2019 which helps to improve PPA on SoC. Owner of DRAM (LP2/LP3/LP4) memory controller and improved performance with support of team members.

RTL DesignDevelopmentTest Plan Bring-upDebuggingPPA improvementDDR memory controller

Engineer

Jul 2017 – Oct 2019 · 2 yrs 3 mos

RTL Design engineer; perform Design Linting ,CDC check , VCS, Novas simulation check , UPF design for low power implementation ,Design Constraint validation, CLP check for RTL and Netlist power intent checks.

Design LintingCDC checkVCSUPF designDesign Constraint validationRTL Design+1

Interim Engineering Intern

Jan 2017 – Jun 2017 · 5 mos

o Worked with front-end design team in DDR-Sub System team on below Design checks :-
RTL compilation and Design lint clean, CDC checking, Synthesizing RTL with Design compiler, Formal verification between Netlist vs RTL, RTL and Netlist CLP check.

RTL compilationDesign lint cleanCDC checkingSynthesizing RTLFormal verificationRTL Design