Avinash Kumar Verma

Software Engineer

Hyderabad, Telangana, India10 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

9 years of expertise in Design Verification.
Strong knowledge of UVM and System Verilog.
Proficient in writing assertions and coverage.

Stackforce AI infers this person is a VLSI Design Verification Engineer with extensive experience in digital design and verification methodologies.

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Skills

Core Skills

Universal Verification Methodology (uvm)PcieVerilog

Other Skills

Functional VerificationSPII2CGPIOUSBRALOpen Verification MethodologyAXICacheSystem verilog AssertionsSVAHVL: System VerilogHDL: VerilogVHDLKnowledge about UVM

About

Summary: ~9 Years of experience in Design Verification (DV). Strong Knowledge on UVM, System Verilog, Verilog, Digital Design. Extensive knowledge of the design concepts and Very-large-scale integration circuit systems. Developed Verification components in System Verilog – UVM Based Environment. Strong Knowledge on UVM Methodology and developed whole environment. Having good exposure in writing System Verilog assertions and Coverage. Writing RTL models in Verilog HDL and Test benches in Verilog. Good understanding of I2C, AHB, APB, PCIe, CXL, Cache Coherency. Experience in Debugging and writing testcases in System Verilog, Verilog. Have knowledge of Python and Perl Scripting.

Experience

10 yrs 1 mo

Total Experience

3 yrs 4 mos

Average Tenure

6 yrs 11 mos

Current Experience

Intel technology

Soc Design Verification Engineer

May 2019 – Present · 6 yrs 11 mos · Hyderabad, Telangana, India · Hybrid

I worked on SOC level GPIO Pads verification.
I am working on PCIE Subsystem Verification.
I worked on RAL for USB Subsystem.
Work on Display IP for some time.

Universal Verification Methodology (UVM)PCIe

Amd

Design Engineer 2

Oct 2017 – May 2019 · 1 yr 7 mos · Hyderabad Area, India

● I was working on CPU crest features (Cache Resident Self-Test)
● My work is to create crest environment and verifying the CPU crest functionality
● Written assertions and worked on coverage.

VerilogUniversal Verification Methodology (UVM)

Wipro technology

VLSI Verification Engineer

Mar 2015 – Oct 2016 · 1 yr 7 mos · Hyderabad Area, India

My responsibility to work there as a verification engineer. I use to write the testcases and Some time I have to write UVM Environment for verifying RTL.
I also worked on Ethernet PHY (GMII/MII/XGMII) and written assertions and functional coverage between PHY and Serdes interface.

VerilogUniversal Verification Methodology (UVM)