Sachin Kotian

DevOps Engineer

Bengaluru, Karnataka, India9 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expert in formal verification for advanced semiconductor designs.
  • Led successful verification projects under high-pressure scenarios.
  • Innovated formal infrastructure and task execution methods.
Stackforce AI infers this person is a Formal Verification Expert in the Semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Formal VerificationFunctional VerificationTest Bench DevelopmentDeadlock VerificationValidation

Other Skills

DDR5 ControllersASIL-D ProjectsBug ReportingCollaborationDebuggingProblem SolvingConnectivity VerificationAssertionsVerilogUniversal Verification Methodology (UVM)SystemVerilogScripting

About

At AMD, my focus as the Formal Lead for server-based low power DDR5 controllers is not just on solving complex verification issues but also on innovating formal infrastructure and task execution methods. Our team's dedication ensures the seamless integration of design, tooling, and engineering support, ultimately advancing the industry's technological frontier. With a Master's in VLSI Design, I apply a rigorous approach to functional verification, leveraging my expertise in Verilog and assertions to enhance AMD's competitive edge. My previous role at Arm honed my leadership in formal methods, contributing to the successful verification of Automotive DSU designs and the identification of critical bugs under high-pressure scenarios.

Experience

9 yrs 8 mos
Total Experience
2 yrs 7 mos
Average Tenure
1 yr 9 mos
Current Experience

Amd

Member of Technical Staff

Jul 2024 – Present · 1 yr 9 mos · Bengaluru, Karnataka, India

  • Leading formal for LP/DDR based server memory controller blocks for deadlock, or functional verification closure
Formal VerificationFunctional VerificationDDR5 Controllers

Arm

2 roles

Staff Engineer

Promoted

Apr 2023 – Jul 2024 · 1 yr 3 mos · On-site

  • Worked on developing MEMSYS formal test bench from scratch for second version of ASIL-D projects. Created test bench by integrating CHI AIP, initial ramp up and worked on solving ASIL-D design problems
  • Responsible for execution of lockstep version of asynchronous CPU bridge. This is scratch project, I worked on every phases of formal cycle thoroughly till the closure. My work helped project in shift left design quality by reporting hundreds of design bugs including deadlock, architecture bugs.
  • Created detailed FV test plan, FV tasks for number of milestones over year half
  • Implemented configurable, scalable test bench and flows, complexity reduction methods
  • Close collaboration with designers and other verification leads
  • Recreated successfully customer reported silicon bugs
  • FV Closure on multiple project releases
  • Team mentoring, Trainings
Formal VerificationTest Bench DevelopmentASIL-D ProjectsBug ReportingCollaboration

Senior Engineer

Nov 2020 – Apr 2023 · 2 yrs 5 mos · On-site

  • Responsible for closure of functional and deadlock verification, clock gating. I have worked on developing interactive helper covers based bug hunting solutions for Interconnect deadlock verification.
  • Implemented end to end checkers for deadlock, Researched and developed helper covers based DBH flows
  • Worked on number of features bring up, projects, Reported 50 plus bugs on Denial of service feature bring up, Recreated successfully customer reported silicon bugs
Functional VerificationDeadlock VerificationBug Reporting

Synopsys inc

Formal Verification Engineer

Mar 2018 – Oct 2020 · 2 yrs 7 mos · Bengaluru Area, India · On-site

  • Worked as formal consultant for complex IP Deadlock verification
  • Individual contributions on validating VC Formal apps, features
  • Worked on wide range VC formal solutions for customer problems
  • Worked on control path problems debugs in FPV, Signoff, connectivity, equivalence check
  • Owner of VC formal signoff apps FPV, FCOV, FTA, deployments
  • Owner of data path app features validations, customer problems solving
Formal VerificationValidationDebugging

Nxp semiconductors

2 roles

Formal Verification Engineer

Jun 2017 – Mar 2018 · 9 mos

  • Worked on contactless security cards IC design formal verification
  • Formal verification problems solving, Knowledge sharing
Formal VerificationProblem Solving

Intern

Jun 2016 – May 2017 · 11 mos

  • Formal verification investigations on unit level verification
  • Formal property verification of reset controller, register read/write, interrupts
  • Connectivity verification
  • Register Verification
  • Unreachable analysis
  • Formal automation using scripts
Formal VerificationConnectivity Verification

Education

Manipal Academy of Higher Education

Master of Engineering (M.Eng.) — VLSI Design

Jan 2015 – Jan 2017

N M A M Institute of Technology, NITTE

Bachelor of Engineering (B.E.) — Electrical and Electronics Engineering

Jan 2010 – Jan 2014

Stackforce found 100+ more professionals with Formal Verification & Functional Verification

Explore similar profiles based on matching skills and experience

GS

Ganapathi S.

Tech Lead

at Intel Corporation

Bengaluru, India25 yrs 5 mos exp
Deepak Garg

Deepak Garg

Director of Engineering

at Siemens EDA (Siemens Digital Industries Software)

Noida, India20 yrs exp
Santosh Thomas

Santosh Thomas

Senior Director, Engineering

at Qualcomm

Bengaluru, India26 yrs 9 mos exp
ASICVLSI
Vishal Mistry

Vishal Mistry

Technical Manager

at eInfochips (An Arrow Company)

Ahmedabad, India17 yrs exp
JG

Jayesh Gaur

Chief Architect of Power Core

at IBM

Bengaluru, India21 yrs 8 mos exp
Computer Architecture
Madhusudhana Reddy

Madhusudhana Reddy

SoC Infrastructure Systems and ARch

at Qualcomm

Bengaluru, India19 yrs 9 mos exp
Power verificationSoC verificationVerification
AS

Amit Sharma

Sr Director, Program Management

at Qualcomm

Bengaluru, India25 yrs 7 mos exp
Neha Bajaj

Neha Bajaj

Power Management IP Architecture Lead

at Google

San Diego, United States19 yrs exp