Aashutosh Garg

Software Engineer

Delhi, India5 yrs 4 mos experience

Highly Stable

Key Highlights

Expert in RTL power estimation and optimization.
Led advanced power analysis workflows at Ansys.
Mentored engineers and delivered global training.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in power analysis and optimization.

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Skills

Core Skills

Power AnalysisPower OptimizationPower Estimation

Other Skills

PowerArtistPTPXRTL powerScriptwritingPower ReductionDebuggingTechnical SupportGlitchLow-power DesignDigital IC DesignApplication-Specific Integrated Circuits (ASIC)Problem SolvingTCLScriptingClock Tree Synthesis

About

I’m a Silicon Design Engineer with expertise in power analysis, optimization, and performance enhancement. I specialize in RTL power estimation and optimization, using tools like PowerArtist and PTPX to deliver efficient, high-performance designs. Over the years, I’ve contributed to power-aware design methodologies, developed advanced features, and mentored engineers at Ansys and AMD. I thrive on solving complex challenges, collaborating with talented teams, and making a meaningful impact on the future of AI and semiconductor design. I’m always excited to learn, grow, and tackle new challenges.

Experience

5 yrs 4 mos

Total Experience

3 yrs 6 mos

Average Tenure

1 yr 9 mos

Current Experience

Amd

Senior Silicon Design Engineer

Jul 2024 – Present · 1 yr 9 mos · Hyderabad, Telangana, India · On-site

Collaborating within the Micro-Architecture team for AI accelerators on power closure, estimation, and design optimization.
Utilize PowerArtist and PTPX for power analysis and optimization, achieving power and performance targets.
Contribute to performance enhancements, ensuring efficient, high-performance designs.
Partner with architects, designers, and verification teams to achieve power, performance, and area (PPA) targets.

Power AnalysisPower OptimizationPowerArtistPTPXRTL power

Ansys

3 roles

Senior Product Specialist

Apr 2024 – Jun 2024 · 2 mos · Noida, Uttar Pradesh, India

Collaborated on future PowerArtist enhancements, focusing on delay-aware glitch analysis and logic inferencing.
Led efforts to refine power analysis workflows, validate new features, and ensure seamless integration.

PowerArtistRTL powerPower AnalysisPower Optimization

Product Specialist II

Apr 2022 – Mar 2024 · 1 yr 11 mos · Noida, Uttar Pradesh, India

Led technical evaluations and power analyses for SoCs with ~50 million instances, delivering early power trend insights.
Developed workflows for power waveform generation and analyzed power dynamics over time.
Played a key role in development of Timing Aware and Physical Aware Power Analysis flow for RTL-to-Gate power correlation.
Led projects, mentored new hires and interns, and delivered global training on advanced power analysis techniques.
Validated PowerArtist features for robustness and reliability.

Power EstimationPower Optimization

Product Specialist

Jul 2020 – Mar 2022 · 1 yr 8 mos · Noida, Uttar Pradesh, India

Contributed to the development of the Advance Buffer Modelling feature to bridge RTL-to-Gate power correlation gaps.
Led RTL-to-Gate power correlation for various designs, covering a diverse range of SoCs and technology nodes (7nm, 5nm, 3nm).
Enhanced QA coverage for PowerArtist, boosting tool reliability.
Supported product engineering and technical activities.

Power EstimationPower Optimization