Surya Pratik Saha — CTO

Over 15 years of experience in the area of Electronic Design Automation technologies (front end, back end, optimization of FPGA Synthesis), Compiler writing, Object model population, Binary dump of Object model, Fast Memory Manager, Customer friendly interface of Object model (API), Fast Expression evaluation. The software is used as front end of different Hardware Description Language (HDL) synthesis/simulation tools. I am passionate on solving critical/complex issues in large scale software programs written in C/C++. Currently working as a senior developer of FPGA Synthesis tool development in a leading EDA company. My role here includes - Monitoring QA issue like unstable result in different platform, Developing Efficient graph based algorithm for FPGA protection and critical Customer handling either by fixing Complex bug or providing quick work around. In past I have managed a small team of front end tools development - Analyzer to parse System Verilog RTL design. This includes - Development and Maintenance of parser, OM population using built-in Memory Manager, Easy to use interface (API) creation, Releasing the product, Porting to Windows Platform, QA and Multiple customers handling. I always ensure quick turn around for any customer issues. Also I actively participate in the System Verilog design community and provides valuable comments in the LRM development. On the management side, I mentored several people joined in the team as fresher, and made them productive. The techniques used include - Knowledge Sharing, regular Code Review, Dedicated Training and Performance Monitoring. Specialties: EDA product development, RTL FPGA synthesis, Graph based algorithm, Run-time and Memory Optimization, Analysis and Elaboration based on HDL, Object Model design, Complex Code debugging, Engineering Teams management, System Verilog, C++, Tcl/TK, QA Tool (purify/valgrind/calgrind)

Stackforce AI infers this person is a highly skilled EDA professional specializing in FPGA synthesis and software development.

Location: Hyderabad, Telangana, India

Experience: 28 yrs 7 mos

Skills

Fpga Synthesis
Eda Product Development
System Verilog

Career Highlights

Over 15 years in Electronic Design Automation.
Expert in FPGA synthesis and optimization.
Strong leadership in mentoring and team management.

Work Experience

AMD

Principal Member of Technical Staff (2 yrs 9 mos)

Senior Member Of Technical Staff (4 yrs 2 mos)

Xilinx

Senior Staff Software Engineer (3 yrs 7 mos)

Staff Software Engineer (6 yrs 1 mo)

Interra Systems

Senior Member of Consulting Staff (14 yrs 1 mo)

Wipro Technologies

Software Engineer (8 mos)

Education

BE at IIEST, Shibpur

Higher Secondary at Barasat Government High School

Secondary at Barasat Government High School

Surya Pratik Saha

CTO

Hyderabad, Telangana, India28 yrs 7 mos experience

Highly Stable

Key Highlights

Over 15 years in Electronic Design Automation.
Expert in FPGA synthesis and optimization.
Strong leadership in mentoring and team management.

Stackforce AI infers this person is a highly skilled EDA professional specializing in FPGA synthesis and software development.

Contact

Skills

Core Skills

Fpga SynthesisEda Product DevelopmentSystem Verilog

Other Skills

Graph based algorithmFPGALogic optimizationCustomer issue handlingGUI developmentQuality assurancePower estimation toolParser developmentCGdbGNU DebuggerTCLDebuggingVHDLVerilog

About

Experience

28 yrs 7 mos

Total Experience

8 yrs 1 mo

Average Tenure

4 yrs 2 mos

Current Experience

Amd

2 roles

Principal Member of Technical Staff

Promoted

Jul 2023 – Present · 2 yrs 9 mos · Hyderabad, Telangana, India

Senior Member Of Technical Staff

Feb 2022 – Present · 4 yrs 2 mos · Hyderabad, Telangana, India

Xilinx

2 roles

Senior Staff Software Engineer

Jul 2018 – Feb 2022 · 3 yrs 7 mos

Staff Software Engineer

Jun 2012 – Jul 2018 · 6 yrs 1 mo

Working in Vivado Synthesis tool as a senior developer. Responsible for quality improvement, feature development and customer interaction.
Key Achievements and Responsibilities:
Development of a solid infrastructure to resolve the unstable synthesis result in different runs of software.
Development of an efficient graph based algorithm to modify FPGA netlist protecting against single event upset ( a kind of real time error).
Critical customer issue handling by providing quick fix or work-around.
Participation in Logic optimization, FPGA inference, System Verilog Interface support either as part of fixing issues or feature support.
Made a major contribution by resolving the unpredictable synthesis result by cleaning up several pointer sorting and hash-map of deleted pointers in core area of software. This is well appreciated in customer level as it was major obstruction of FPGA development using Vivado software.

Graph based algorithmFPGASystem VerilogLogic optimizationCustomer issue handlingFPGA Synthesis+1

Interra systems

Senior Member of Consulting Staff

May 1998 – Jun 2012 · 14 yrs 1 mo · Kolkata Area, India

Joined as Software Engineer in service project of Sente Inc. in Interra (previously known as Delsoft).
Key responsibilities:
GUI development of power estimation tool.
Quality assurance (run-time and memory reduction).
Development of a new Power Reduction tool.
The service project is over in 2001 Oct.
Then I jointed in Cheetah to develop SuperLog (Later known as System Verilog) language
analyzer.
Key Achievements and Responsibilities:
Made Cheetah as System Verilog standard analyzer (parsing and elaboration).
Complete architecture development of user friendly and easily portable software.
Risk and mitigation planning, implementation and progress monitoring along with mentoring.
Helped and guided customers to upgrade their software as language evolves.
Significant reduction of run-time and memory footprint by cleaning up the core object model.
Made major business impact by providing qualitative and quantitative customer support in quick time-frame.
Co-ordinate with System Verilog LRM committee for future development of language and resolving ambiguities.