Ronak Ratanpara

Software Engineer

Bengaluru, Karnataka, India9 yrs 10 mos experience

Highly Stable

Key Highlights

Expertise in VLSI and EDA solutions.
Proven track record in PPA improvements.
Strong customer engagement and collaboration.

Stackforce AI infers this person is a Semiconductor expert with a focus on EDA solutions and VLSI design.

Contact

Skills

Core Skills

SynthesisPhysical Design

Other Skills

Logic SynthesisPhysical SynthesisSystem on a Chip (SoC)CommunicationCTSClock Tree SynthesisRoutingSignoffFloorplanningPlacementTeam playerCustomer EngagementProliferationFlow EvaluationPPA

About

At Cadence Design Systems, my current role as Principal Application Engineer blends my expertise in VLSI with the responsibility of deploying cutting-edge EDA solutions. With a Master's degree in VLSI and Embedded System Design, I navigate the complexities of synthesis, physical design, and signoff with ease, striving for peak performance in lower technology node designs. Our team's achievements in methodological advancements for design closure and PPA improvements reflect our commitment to technical excellence and customer satisfaction. My approach is both data-driven and quality-focused, ensuring that strategic customer accounts benefit from our collaborative efforts in technology deployment and problem-solving.

Experience

9 yrs 10 mos

Total Experience

3 yrs

Average Tenure

9 mos

Current Experience

Mediatek

Staff Engineer

Jul 2025 – Present · 9 mos · Bengaluru, Karnataka, India · On-site

Cadence design systems

3 roles

Principal Application Engineer

Jun 2024 – Jun 2025 · 1 yr

Working as a pre-sale’s technology expert primarily responsible for evaluation, Deployment and proliferation of cutting-edge EDA solutions at strategic customer accounts.
Hand-on experience in Synthesis, Physical Design, and signoff on lower technology node PPA centric designs at multiple customers.

Logic SynthesisPhysical SynthesisSynthesisPhysical Design

Lead Application Engineer

Promoted

Jun 2021 – Jun 2024 · 3 yrs

Have successfully deployed scalable Genus & Innovus methodologies for design closure and PPA
improvements for complex multi-million gate designs (CPU/GPU/SoC) across multiple customer.
Expertise in handling advanced deep sub-micron technology node designs.
Served as an efficient interface between customer and R&D for addressing existing tool bugs and
enabling new features.
Actively worked on Synthesis & P&R flow methodology with Local Customers for PPA
improvement.
Delivered Synthesis-EDA pre-Sales training to multiple customers.

System on a Chip (SoC)CommunicationSynthesisPhysical Design

Senior Application Engineer

Oct 2017 – May 2021 · 3 yrs 7 mos

As Synthesis/STA Engineer, working closely with cadence customers on evaluation, benchmarks, and
flow implementation
Work Closely with R&D in testing Beta releases.

Logic SynthesisPhysical SynthesisSynthesisPhysical Design