Burhanuddin Dhandhukawala

Software Engineer

Greater Delhi, Delhi, India5 yrs 7 mos experience
Most Likely To Switch

Key Highlights

  • Expertise in Verilog and Physical Design.
  • Strong background in Logic Synthesis and Physical Verification.
  • Experience in high-frequency trading hardware design.
Stackforce AI infers this person is a Hardware Design Engineer with expertise in VLSI and Physical Design.

Contact

LinkedIn

Skills

Other Skills

Design Rule Checking (DRC)Layout Versus Schematic (LVS)Logic SynthesisPNRPhysical DesignPhysical VerificationShell ScriptingSignoffVerilog

About

Everyday is Sunday. I work on Sundays.

Experience

High frequency trading

Hardware Design Engineer

Aug 2023 – Present · 2 yrs 7 mos · On-site

Ceremorphic, inc.

Digital Design Engineer

Dec 2022 – Jul 2023 · 7 mos · Hyderabad, Telangana, India · On-site

Cadence design systems

Software Engineer

Jul 2021 – Dec 2022 · 1 yr 5 mos · Bengaluru, Karnataka, India · On-site

Einfochips (an arrow company)

Physical Design Engineer

Jul 2017 – Jul 2018 · 1 yr · Ahmedabad, Gujarat, India

Eitra - einfochips training & research academy ltd

Physical Design Trainee

Jan 2017 – Jul 2017 · 6 mos · Ahmedabad, Gujarat, India

Education

Indian Institute of Technology, Bombay

Master of Technology - MTech — Microelectronics and VLSI

Jul 2018 – Jul 2021

Indus University

Bachelor of Technology (B.Tech.) — Electrical and Electronics Engineering

Jan 2013 – Jan 2017

Stackforce found 100+ more professionals with Design Rule Checking (DRC) & Layout Versus Schematic (LVS)

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