kirankumar dammavalam — Software Engineer
Currently handling a sub system that has 3 partitions from netlist to gds. proven experience in achieving convergence on critical blocks for very high frequency 3Ghz GPU designs in TSMC 5nm technology node. SOC IO-Ring planning and support for package design team, SOC Floor Planning, Power- Planning, PNR, Custom integration for Analog modules(~70%) in SOC, Mask Finishing, Physical Verification ( DRC, LVS, Antenna and DFM checks). Tools: cadence innovus, NRHF(Nano route high frequency) for custom routing in innovus, Mentor Calibre
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in high-frequency GPU architecture.
Experience: 12 yrs 7 mos
Skills
- Static Timing Analysis
- System On A Chip (soc)
- Floorplanning
- Place & Route
Career Highlights
- Expert in high-frequency GPU design at TSMC 5nm.
- Proven track record in achieving timing closure.
- Strong background in SoC design and physical verification.
Work Experience
Intel Corporation
Graphics physical design Engineer (4 yrs)
Cadence Design Systems
Lead Design Engineer (2 yrs)
STMicroelectronics
Tech Lead (1 yr 10 mos)
Senior Design Engineer (1 yr 11 mos)
Design Engineer (2 yrs)
Intern- Process Design Kit (10 mos)
Education
Master's Degree at Manipal Institute of Technology
Bachelor's Degree at Gudlavalleru Engineering College
Intermediate at Sri Chaitanya junior college, guntur
High School at A.P.R School, Nizampatnam, guntur
