Neetu Batra

Director of Engineering

Noida, Uttar Pradesh, India26 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

15 years of experience in semiconductor design.
Expert in Backend timing closure of ARM blocks.
Proficient in advanced technology nodes like 7nm and 8nm.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in backend design and timing closure.

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Skills

Core Skills

System On A Chip (soc)

Other Skills

STATiming ClosureInnovusPrime TimeStarRC-XTP&RFloor PlanPlacementCTSRoutingExtractionLVSDRCFormal VerificationICC

About

• 15 years of total experience in Place & Route (PNR), Timing closure, Floor Plan, STA, CTS, Timing ECO, Parasitic Extraction, Signial Integrity analysis, Power optimization, Physical verification (DRC/LVS), Manual ECO. • Working in Qualcomm Bangalore since May 2018, in STA and Timing closure. • Experience in latest nodes of 7nm, 8nm and 16nm • Expert in Backend timing closure of ARM Blocks. • Basic Knowledge of Library Development, Full Custom Layouts. • Thorough understanding of the various tools used in P&R domain

Experience

26 yrs 8 mos

Total Experience

4 yrs 10 mos

Average Tenure

6 yrs 1 mo

Current Experience

Intel corporation

SOC Design Manager

Mar 2020 – Present · 6 yrs 1 mo · Bengaluru, Karnataka, India

System on a Chip (SoC)

Qualcomm

Staff Engineer

May 2018 – Nov 2022 · 4 yrs 6 mos · Bangalore

Working in 7nm and 8 nm Tech-node in STA and Timing closure

System on a Chip (SoC)

Hcl technologies

Sr. Technical Manager

Nov 2016 – Apr 2018 · 1 yr 5 mos · Noida Area, India

Lead the P&R Team for the successful implementation and timing closure of various blocks of approx. 3million gate count
Technology : 16nm, 40nm
Tools : Innovus, Prime Time, StarRC-XT

System on a Chip (SoC)InnovusPrime TimeStarRC-XT

Slenderrex it design systems pvt. ltd.

Sr. Account Manager

Feb 2012 – Oct 2016 · 4 yrs 8 mos · Noida Area, India

Account Managemnt And Business Development

St-ericsson

Tech Lead

Mar 2009 – Feb 2012 · 2 yrs 11 mos · Noida Area, India

ARM1176 Arm core 65nm LP Technology (410 MHz)
A966CM Arm core 65nm LP Technology (380 MHz)
CORTEX R4 Arm Core 40nm (416 Mhz)
ARM CORTEXR4CM 65nm LP (380 Mhz)
Responsibility : Floor Plan, Placement, CTS, Routing, STA, Timing Closure, Extraction, LVS, DRC, Formal verification

System on a Chip (SoC)

Stmicroelectronics

Design Engineer

Jun 1999 – Mar 2009 · 9 yrs 9 mos · Noida Area, India

Projects :
Modem (130 nm)
ARM946 core in 90nm. (220 MHz)
MIPS core in 90nm (220 MHz)
Responsibility : Floor Plan, Placement, CTS, Routing, STA, Timing Closure, Extraction, LVS, DRC, Formal verification
Full Custom Layout Design.
Reverse Engineering of various FPGAs

System on a Chip (SoC)