Anand Anantha Narayanan

CTO

Bengaluru, Karnataka, India22 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Power Grid Design and Electrical Modeling
  • Leadership in Electrical Quality Signoff at Intel
  • Extensive experience in System on a Chip design
Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on power delivery and electrical convergence.

Contact

LinkedIn

Skills

Core Skills

Power DeliveryElectrical MethodologySystem On A Chip (soc)Electrical Convergence

Other Skills

PD methodolgyAttention to DetailSoC DesignVery-Large-Scale Integration (VLSI)EDAApplication-Specific Integrated Circuits (ASIC)SemiconductorsTCLDebuggingIntegrated Circuits (IC)Structured Problem SolvingPhysical DesignPerlStatic Timing AnalysisProcessors

About

Expert in Power Grid Design, Analysis and Signoff Specialist in Electrical Modeling and Extraction Cross Functional leader in Electrical Quality Signoff

Experience

22 yrs
Total Experience
11 yrs
Average Tenure
21 yrs 7 mos
Current Experience

Intel corporation

3 roles

Principal Engineer

Promoted

Apr 2022 – Present · 4 yrs

  • Power Delivery, EMIR, 3DIC
  • Electrical Methodology and Convergence
  • SRC Advisory Board Member
PD methodolgyAttention to DetailPower DeliveryElectrical Methodology

System-on-Chip Design Engineer

Promoted

Aug 2018 – Apr 2022 · 3 yrs 8 mos

  • Electrical convergence lead for Xeon Server, Datacenter graphics Server SOCs: 2018 – 2019
  • Xeon Server Design Backend convergence lead across horizontal Domains: 2020-Present
PD methodolgyAttention to DetailSystem on a Chip (SoC)Electrical Convergence

Senior Component Design Engineer

Aug 2004 – Jul 2018 · 13 yrs 11 mos

  • CAD Flows (Device level timing, analysis and simulation flows): 2004-2006
  • CAD Flows (Device/cell/soc level RC extraction, High speed global Clock Analysis flows): 2007-2012
  • CAD Flows (SOC PDN verification, Device/Stdcell/SOC Reliability flows): 2012-2015
  • Multi-die stacking signoff enablement, SD flows lead (RTL2GDS, Signoff): 2016-2018

Sasken

Design Engineer

Mar 2004 – Aug 2004 · 5 mos

  • ASIC Flow validation for Texas Instruments

Amd

2 roles

Co-op Engineer

May 2002 – Aug 2002 · 3 mos · Austin, Texas Metropolitan Area

  • Add-on board Schematics, layout design for mobile processor validation

Co-op Engineer

Aug 2001 – Dec 2001 · 4 mos · Austin, Texas Metropolitan Area

  • Clock Controller – RTL Design, Implementation, Validation on Lattice PLD.

Education

Rensselaer Polytechnic Institute

MS

Jan 2000 – Jan 2002

PSG College of Technology

BE — Electrical and Electronics Engineering

Jan 1995 – Jan 2000

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