PRASANNA KUMAR GADIYARAM

Director of Engineering

Hyderabad, Telangana, India25 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in ASIC/FPGA Synthesis and Design-For-Test methodologies.
Proficient in multiple EDA tools for verification and synthesis.
Extensive experience in debugging and yield analysis for complex designs.

Stackforce AI infers this person is a highly skilled ASIC/FPGA Design Engineer with extensive experience in DFT and verification methodologies.

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Skills

Core Skills

Asic/fpga SynthesisDesign-for-testDft ToolsRtl VerificationFpga DesignVlsi DesignEmbedded Systems

Other Skills

VERILOGVHDLSystem VerilogTCLJTAGATPGYield AnalysisScan insertionJTAG logicBIST generationFPGABoard designRTL codingVerificationSynthesis

About

-- Immensely empowered with the knowledge of VERILOG, PLI, VHDL, system verilog, perl and tcl -- Scan insertion using full, parallel, and partial scan methodology. -- Creating BIST controller for testing the embedded memory blocks. -- Logic BIST generation and pattern creation . -- ATPG vectors generation for testing all types of faults (stuck-at, at-speed). -- EDT vectors(test compression) generation for testing the manufacturing defects. -- ATE vector translation (STIL/WGL). Yield Analysis. -- Creating JTAG controller for debugging the boundaries. -- DFT tools worked on: TestKompress, FastScan, DFTAdvisor, MBISTArchitect, LBISTArchitect, BSDArchitect, YieldAssisit. -- Experience on Mentor Calibre physical verification tool. -- Expericnce on sierra Place and route tool. -- Experience in CPF, UPF, SDC (Synopsys Design constrains), SDF (Standard delay format). -- Experience on Xilinx/altera FPGAs and CPLD based designs. -- Analog and Digital circuits designing, Board designing, board level and chip level testing. --EDA tools : ModelSim, NC-Verilog, Synopsys VCS, Design Compiler, Precision synthesis, Synplify-Pro, Amplify, Primetime, Xilinx ISE , Altera Maxplus/Quartus II, System Generator, Chipscope Pro, Actel Libero. Specialties: Verilog, VHDL, System Verilog, ASIC/FPGA Synthesis, STA, Design-For-Test, ASIC/FPGA place and route, C, C++, Perl, tcl

Experience

25 yrs 7 mos

Total Experience

4 yrs 7 mos

Average Tenure

4 yrs 2 mos

Current Experience

Amd

Director Silicon Design Engineering

Feb 2022 – Present · 4 yrs 2 mos · Hyderabad, Telangana, India · On-site

VERILOGVHDLSystem VerilogTCLDFT toolsJTAG+4

Xilinx

IC DESIGN MANAGER

Oct 2009 – Sep 2023 · 13 yrs 11 mos

Mentor graphics

DFT Lead Engineer

Aug 2004 – Oct 2009 · 5 yrs 2 mos

Working as Lead Engineer in Mentor Graphics Inida Pvt Ltd.
Involved in below activities.
Debugging the customer designs issues, identifying the design problems, and providing the solutions. Working on scan insertion, creating patterns all types of faults (stuck-at, transition, path delay, bridge, iddq faults) for multi million gate designs. Timing aware pattern generation. Low power pattern generation. Simulation mismatch debugging, Writing named capture procedures. Memory bist generation using different algorithms, Diagnostics logic, built in self analysis, scan logic. Generating JTAG logic, Performing yield analysis.
Presenting the design flows and tool features.
Worked on multi million gate designs from all major chip developers, Worked on memories from different vendors.
Verified the ATPG and pattern compression tool features like support for Timing aware pattern generation, low power design, low power shift and capture, Simulation mismatch debug, Embedded multiple detect, Clock gating, Named capture procedures, at-speed fault detection, Glitch detections, False path and multicycle path based pattern generation, Embedded Deterministic test, Modular EDT, Fault grouping,
Verified BIST tool features like Scan insertion, Logic bist generation, Test point insertion, Memory bist generation, Debugging the code, Memory row and column repair and diagnosis, Boundary scan cell insertion for all types of ports.

Scan insertionATPGJTAG logicBIST generationYield analysisDesign-For-Test+1

Digipro

Design Engineer

Mar 2003 – Aug 2004 · 1 yr 5 mos

Writing verilog/VHDL code for FPGA based designs, RTL Verification, FPGA board design and testing, Place and route.

VerilogVHDLFPGARTL VerificationBoard designASIC/FPGA Synthesis

Sitec electronics

Design engineer

May 2002 – Mar 2003 · 10 mos

Designing Xilinx, Altera and lattice based FPGA and CPLD boards.
Training on Xilinx, Altera tools, FPGA resource usage and board designs.
RTL coding, Verification, synthesys, Place & route, Timing Analysis 8-bit microcontrollers.
Worked in Virtex, spartan2, coolrunner, cyclone, stratix devices,

FPGARTL codingVerificationSynthesisTiming AnalysisASIC/FPGA Synthesis+1

Nk electronics

Design Engineer

Sep 2000 – May 2002 · 1 yr 8 mos

Worked on VLSI projects RTL coding and verification (Verilog,VHDL).
Worked on Board designing and testing, Analog, Digital projects 8bit microcontrollers and embedded projects

VerilogVHDLBoard designingTestingEmbedded projectsVLSI Design+1