Arpan Sircar

CTO

Bengaluru, Karnataka, India25 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Senior Principal Engineer with extensive experience in IC design.
Expertise in Physical Design and Timing Closure.
Strong background in EDA tools and methodologies.

Stackforce AI infers this person is a semiconductor design expert with a focus on ASIC and VLSI technologies.

Contact

Skills

Other Skills

Physical DesignTechnical Account ManagementASICICEDAClock Tree SynthesisSoCTCLVLSIStatic Timing AnalysisTiming ClosureSignal IntegrityDebuggingLow-power DesignIntegrated Circuit Design

About

Having a great time

Experience

25 yrs 7 mos

Total Experience

5 yrs 1 mo

Average Tenure

9 yrs 6 mos

Current Experience

Intel corporation

3 roles

Principal Engineer

Jun 2017 – Apr 2020 · 2 yrs 10 mos

Lead, Methodology & Tech Readiness

Oct 2016 – Present · 9 yrs 6 mos

Senior Principal Engineer

Oct 2016 – Present · 9 yrs 6 mos

Cadence design systems

Solutions Architect

Aug 2015 – Oct 2016 · 1 yr 2 mos · Bengaluru Area, India

Mentor graphics

2 roles

Technical Manager, IC Implementation

Promoted

Aug 2013 – Jul 2015 · 1 yr 11 mos · Bengaluru Area, India

P&R Product Specialist

Aug 2009 – Aug 2013 · 4 yrs · Bengaluru Area, India

Magma design automation

Staff Engineer / Technical Account Manager

Mar 2004 – Aug 2009 · 5 yrs 5 mos

Synopsys inc

2 roles

Applications Consultant

Jun 2002 – Jan 2004 · 1 yr 7 mos

Product Engineer

Jun 2000 – Jun 2002 · 2 yrs

Education

Indian Institute of Science (IISc)

M.Tech — Artificial Intelligence

Aug 2022 – Apr 2025

Indian Institute of Technology, Kanpur

Bachelor of Technology — Electrical Engineering

Jan 1996 – Jan 2000

Birla Senior Secondary School, Pilani

Jan 1994 – Jan 1996

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