Aditya Patil

Product Engineer

Bengaluru, Karnataka, India1 yr 11 mos experience

Key Highlights

Proficient in STA engineering and timing analysis.
Hands-on experience with Synopsys PrimeTime and scripting.
Completed projects in analog and digital VLSI design.

Stackforce AI infers this person is a VLSI Design Intern with a focus on physical design and verification in the semiconductor industry.

Contact

Skills

Core Skills

Sta EngineeringPhysical DesignDesign And Verification

Other Skills

Synopsys PrimeTimePERLTCLDigital DesignsVerilogncverilogCadencePython (Programming Language)Embedded CC (Programming Language)GitHubEmbedded Systems

About

I am a CPU Physical Design Intern at Intel in ACE India (P-Core) working as a STA engineer. Working on Synopsys PrimeTime tool for timing analyses. Proficient in PERL/TCL scripting to analyze and generate tool reports. I am also pursuing my Master's degree in VLSI-Design at Vellore Institute of Technology, with an expected graduation date of August 2024. I have completed several projects on analog and digital VLSI, using various tools and technologies, such as Cadence Virtuoso, UMC180nm, and ncverilog.

Experience

1 yr 11 mos

Total Experience

1 yr 11 mos

Average Tenure

1 yr 11 mos

Current Experience

Intel corporation

2 roles

CPU Physical Design Engineer

Jun 2024 – Present · 1 yr 11 mos

CPU Physical Design Intern

Jul 2023 – Jun 2024 · 11 mos

STA Engineer

Synopsys PrimeTimePERLTCLSTA EngineeringPhysical Design

L&t technology services limited

Embedded Engineering Intern

Jan 2022 – May 2022 · 4 mos · Mysuru, Karnataka, India · On-site

Entuple technologies pvt. ltd.

Engineering Intern

May 2020 – Jul 2020 · 2 mos · Bangalore

Completed 6 weeks internship on "Design and Verification Using Verilog" @EntupleTechnologies. During this internship worked on ncverilog tool from Cadence Designs Systems.

Digital DesignsVerilogncverilogDesign and Verification