Yash Bhasker

Software Engineer

Hyderabad, Telangana, India11 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in ARM architecture for automotive applications.
Proficient in SystemC and memory controller development.
Strong background in validation and testing methodologies.

Stackforce AI infers this person is a specialist in Automotive and Semiconductor industries with a focus on validation and development.

Contact

Skills

Core Skills

SystemcAutomotive VdkMemory ControllerInterconnect IntegrationMemory Controller Validation

Other Skills

TLMbare metal software testingLinux boot bring upGeneric Memory controllercustom schedulercustom arbiterArteris FlexNoCNCore Interconnectcycle accurate modelvalidationResearchUnix Shell ScriptingDebuggingPerlSystem on a Chip (SoC)

About

Virtual Development Kit(VDK) Looking after development of Virtual Development Kit(VDK) based on ARM architecture for Automotive and application development use case. Responsible for end to end validation of the VDK using bare metal software and unit level testing Interconnect Developed a flow to integrate the Arteris FlexNoC and NCore Interconnect with Synopsys Platform Architect tool to help the Architect for Architecture exploration use case Memory Controller Good understanding of Generic and Cycle accurate memory controller and JEDEC DRAM Memory protocol. Hands-on Expertise: - AXI, JEDEC DDR3, DDR4, LPDDR4/4X, DDR5, LPDDR5 Protocol - C, C++, SystemC - TCL, Bash,Python - Synopsys Platform Architect Ultra, Core Consultant, Virtualizer, Arteris FlexNoC - Linux OS

Experience

11 yrs 7 mos

Total Experience

4 yrs

Average Tenure

3 yrs 7 mos

Current Experience

Amd

Member of Technical Staff

Sep 2022 – Present · 3 yrs 7 mos · Hyderabad, Telangana, India

Synopsys inc

3 roles

Senior R&D Engineer II

Dec 2021 – Sep 2022 · 9 mos

Senior R&D Engineer 1

Jan 2019 – Dec 2021 · 2 yrs 11 mos

Virtual platform, Automotive VDK based on ARM architecture . Developed SystemC/TLM based virtual Peripherall Models like PWM(Pulse width Modulation), SENT(Single Edge Nibble Transmission) ,I2C, System Timer. Bare metal software testing, Linux boot bring up on VDK

SystemCTLMbare metal software testingLinux boot bring upAutomotive VDK

R&D Engineer II

Dec 2015 – Jan 2019 · 3 yrs 1 mo

Worked on the Generic Memory controller solution which contains the custom scheduler , custom arbiter and custom inorder scheduler. Worked on integrating Arteris FlexNoC and NCore Interconnect in Synopsys Platform Architect tool

Generic Memory controllercustom schedulercustom arbiterArteris FlexNoCNCore InterconnectMemory Controller+1

Synopsys india pvt ltd

R&D Engineer I

Jul 2014 – Oct 2015 · 1 yr 3 mos · Noida, Uttar Pradesh, India

Worked on the SystemC cycle accurate model of DWC_DDR_uMCTL2 Synopsys Memory controller. I was primarily responsible for the full validation of the memory controller solution. Developed generic flows which can help in quick validation the cycle accuracy and functionality of the model.

SystemCcycle accurate modelvalidationMemory Controller Validation