R

Ramakrishna Apsingikar

Software Engineer

Union City, California, United States20 yrs 10 mos experience
Highly Stable

Key Highlights

  • Senior R&D Engineer with extensive EDA experience
  • Expertise in Verilog and simulation technologies
  • Proven track record in developing advanced verification tools
Stackforce AI infers this person is a Senior EDA Engineer with a strong focus on verification technologies.

Contact

LinkedIn

Skills

Core Skills

EdaVerilog

Other Skills

Data StructuresFunction Coverage technologySystemC simulationPioneer-NTB

Experience

20 yrs 10 mos
Total Experience
20 yrs 10 mos
Average Tenure
20 yrs 10 mos
Current Experience

Synopsys inc

3 roles

R&D Engineer Sr.Staff

Jul 2019 – Present · 6 yrs 9 mos

EDAVerilogData Structures

R&D Engineer, Sr. Staff

Jun 2012 – Jul 2019 · 7 yrs 1 mo

R&D Engineer

Jun 2005 – Present · 20 yrs 10 mos

  • Working as Sr. R&D Engineer with Verification Group on Verilog Compiler Simultor(VCS).
  • I've worked on different components of this tool which include Function Coverage technology and SystemC simulation and Pioneer-NTB.
VerilogFunction Coverage technologySystemC simulationPioneer-NTB

Education

Indian Institute of Technology, Kanpur

M.Tech — Computer Science

Jan 2003 – Jan 2005

University College of Engineering, Osmania University (Autonomus)

B.E — Computer Science

Jan 1999 – Jan 2003

Kakatiya Junior College, Nizamabad

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