Srishailam K

Software Engineer

Hyderabad, Telangana, India4 yrs 10 mos experience

Highly Stable

Key Highlights

Expert in DFT and silicon validation.
Proficient in ATPG and digital IC design.
Strong background in scripting and simulation tools.

Stackforce AI infers this person is a DFT Engineer with expertise in digital IC design and silicon validation.

Contact

Skills

Core Skills

AtpgSilicon ValidationDftDigital Ic Design

Other Skills

Vmin issues diagnosisTest Pattern GenerationSimulation failure fixingIddq validationPAGLSScan chain tracingPower Switch Topoff vectorsAMBA protocolVerilogEngineeringC (Programming Language)Arduino IDEProteusNI MultisimAMBA AHB

About

Currently, working in Qualcomm as SoC DFT Engineer. Pursued M.Tech from IIT Kharagpur in Electrical Engineering. Proficient in Digital IC design,PLDRC, Iddq, SAF, scan chain tracing, Power Aware Gate Level Simulations and non scan cell review. Scripting languages: Python, Perl, Linux, TCL Tools: Spyglass, Tessent, Cadence Virtuoso, Quartus prime, LTSpice

Experience

4 yrs 10 mos

Total Experience

3 yrs 5 mos

Average Tenure

1 yr 5 mos

Current Experience

Amd

Sr. Silicon Design Engineer

Dec 2024 – Present · 1 yr 5 mos · Hyderabad, Telangana, India · On-site

Qualcomm

2 roles

Senior Engineer

Promoted

Dec 2023 – Dec 2024 · 1 yr

Handled diagnosis of post silicon issues from P0 phasing to P3 and fixed Vmin issues by generating
low toggle vectors.
Owned execution of Automatic Test Pattern Generation (ATPG) for 18 CBDFT blocks complex blocks like camera, multimedia subsystem, audio and videos subsystems
Fixed simulation failures in TDF by fixing clock monitoring failures at core level and SoC level in SSN
architecture in all the valid corners (like lsvs, svs, nom and tur).
Delivered quality ATPG test vectors for SAF and TDF to the test engineers to detect manufacturing
defects on silicon on time.

ATPGVmin issues diagnosisTest Pattern GenerationSimulation failure fixingSilicon validation

SoC DFT Engineer

Jul 2021 – Dec 2023 · 2 yrs 5 mos

Working on ATPG based on SSN architecture
Handled Iddq validation for modem chip
Worked on PAGLS, serial simulations and parallel simulation for TDF on modem chip
Owned Non scan cell validation for modem chip and smart watch chip
Owned PLDRC checks for automobile chip
Worked on Scan chain tracing, Coverage runs for SAF
Generated Power Switch Topoff vectors for all power switches

ATPGIddq validationPAGLSScan chain tracingPower Switch Topoff vectorsDFT+1

Indian institute of technology, kharagpur

Teaching Assistant

Dec 2020 – May 2021 · 5 mos · Kharagpur, West Bengal, India

Teaching assistant for Embedded Systems Lab, Measurement and Electronic Instrumentation lab and Electrical Technology course for undergraduate students during the academic year 2021.