Dilip kumar s

Software Engineer

Bengaluru, Karnataka, India10 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in ASIC and FPGA design flows.
Proficient in Verilog HDL and SystemVerilog.
Strong background in verification methodologies.

Stackforce AI infers this person is a VLSI design engineer with expertise in ASIC and FPGA development.

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Skills

Core Skills

Asic DesignFpga Design

Other Skills

ASIC design flowFPGA design flowRTL models in Verilog HDLTestbenches in SystemVerilogUVMverification methodologiesEDA toolsRTL CodingFSM based designSimulationCode CoverageFunctional CoverageSynthesisStatic Timing AnalysisABV-SVA

About

 Good understanding of the ASIC and FPGA design flow  Extensive experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog and UVM.  Very good knowledge in verification methodologies.  Experience in using industry standard EDA tools for the front-end design and verification RTL Coding, FSM based design, Simulation,Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, ABV- SVA.  Scripting language: perl(basics).

Experience

10 yrs 6 mos

Total Experience

3 yrs 6 mos

Average Tenure

7 yrs 10 mos

Current Experience

Samsung r&d institute india - bangalore private limited

Senior Engineer

Jun 2018 – Present · 7 yrs 10 mos · Bangalore

ASIC design flowFPGA design flowRTL models in Verilog HDLTestbenches in SystemVerilogUVMverification methodologies+12

Mindlance technologies

Verification Engineer

Feb 2017 – May 2018 · 1 yr 3 mos · India

Maven silicon

VLSI TRAINEE at maven silicon

Sep 2015 – Feb 2017 · 1 yr 5 mos · banglore

Good understanding of the ASIC and FPGA design flow
Extensive experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog and UVM.
Very good knowledge in verification methodologies.
Experience in using industry standard EDA tools for the front-end design and verification
worked on router 1x3 and SPI protocols.

ASIC design flowFPGA design flowRTL models in Verilog HDLTestbenches in SystemVerilogUVMverification methodologies+5