Sumiya Shaik

Software Engineer

Bengaluru, Karnataka, India6 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in Static Timing Analysis and Synthesis.
Achieved first-pass timing closure for complex SoCs.
Mentored teams in STA methodologies and automation.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Static Timing Analysis and Synthesis.

Contact

Skills

Core Skills

Static Timing AnalysisSynthesis

Other Skills

Logic & Physical aware SynthesisPPA optimizationPythonTclShellTimingPerlCrosstalk-aware timingLow-power timing analysisSynopsys PrimeTimeSynopsys Design CompilerCadence InnovusTiming AnalysisCadence EncounterLEC

About

Highly skilled STA Engineer with 6+ years at Mediatek, specializing in Static Timing Analysis (STA) and Logic & Physical aware Synthesis for complex SoCs at advanced FinFET nodes (5nm, 4nm, 3nm). Proven expert in achieving timing closure, PPA optimization, and driving design robustness through advanced methodologies and automation (Python, Tcl, Shell).

Experience

6 yrs 9 mos

Total Experience

6 yrs 9 mos

Average Tenure

6 yrs 9 mos

Current Experience

Mediatek

3 roles

Staff Engineer

Jun 2024 – Present · 1 yr 10 mos

Static Timing AnalysisLogic & Physical aware SynthesisPPA optimizationPythonTclShell+1

Senior Engineer: Synthesis & STA

Jul 2019 – Jul 2025 · 6 yrs

Led timing sign‐off and timing closure for multiple complex SoCs (Flagship mobile pro‐
cessors, Automotive chipsets) at advanced FinFET nodes (4nm, 3nm), leveraging Synopsys
PrimeTimeto achieve first‐pass timing closure and meet stringent performance targets.
Spearheaded the development and implementation of advanced STA methodologies,
including POCV integration, Crosstalk‐aware timing, and low‐power timing analysis (DVFS),
resulting in 20% reduction in timing closure cycles.
Drove logic synthesis and physical synthesis for critical, high‐performance IP blocks (Modem
& SOC IPs), utilizing Synopsys Design Compiler and Cadence Innovus to optimize PPA (Power,
Performance, Area).
Mentored and technically guided teams of 3 to 7 junior/senior engineers, fostering skill
development in STA and Synthesis, and ensuring adherence to project timelines.
Collaborated cross‐functionally with RTL design, Physical Design, DFT teams to identify,
debug, and resolve complex timing, synthesis, and integration issues, ensuring seamless chip
integration and successful tape‐outs.

TimingPerlStatic Timing AnalysisSynthesisCrosstalk-aware timingLow-power timing analysis+1

Intern

Jan 2019 – Jun 2019 · 5 mos

Supported senior engineers in debugging minor timing violations and analyzing timing
reports, contributing to early‐stage timing closure activities.
Developed basic Tcl scripts for data extraction and report generation, improving efficiency
in routine timing analysis tasks.
Contributed to logic synthesis efforts and performed Conformal Equivalence Checking (LEC)
on foundational digital modules, specifically focusing on leakage power reduction .