Srivardhan Reddy Vedere

Software Engineer

Noida, Uttar Pradesh, India13 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in RTL design and power management.
  • Strong background in verification methodologies.
  • Hands-on experience with emulation and analysis tools.
Stackforce AI infers this person is a semiconductor design engineer with expertise in RTL design and verification.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignPower ManagementDesign VerificationVerificationEmulation

Other Skills

Voltage Domain Crossover RTL generationUPF GenerationStatic Power ChecksPower aware SynthesisSynthesisLECLintCDCEmulation toolsPower aware analysisSystemVerilogUVMPerlCProgramming

About

Experienced Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Verilog, VHDL,Design For Power,Synthesis,Lint,CDC,System Verilog ,Universal Verification Methodology (UVM),Perl and PSoC. Strong engineering professional with a Master of Engineering (M.Eng.) focused in Microelectronics from Birla Institute of Technology and Science.

Experience

13 yrs 3 mos
Total Experience
6 yrs 7 mos
Average Tenure
12 yrs 9 mos
Current Experience

Amd

3 roles

Senior Design Engineer

Promoted

Jul 2017 – Present · 8 yrs 10 mos

Design Engineer2

Feb 2015 – Jul 2017 · 2 yrs 5 mos

  • Worked on Voltage Domain Crossover RTL generation and UPF Generation for Tiles ,delivery of SOC level UPF and Static Power Checks at SOC and Tile level and also Power aware Synthesis/LEC related issues
Voltage Domain Crossover RTL generationUPF GenerationStatic Power ChecksPower aware SynthesisRTL DesignPower Management

Design Engineer1

Jul 2013 – Jan 2015 · 1 yr 6 mos

  • Execution of RTL Integration and Implementation activities like Synthesis,LEC,Lint and CDC
SynthesisLECLintCDCRTL DesignDesign Verification

Stmicroelectronics

Intern

Jan 2013 – Jun 2013 · 5 mos · Greater Noida

  • Gained hands on experience with emulation and power aware analysis tools like Tbx, questasim.
  • Worked on Veloce2 Emulation Systems.
  • Implemented the DPI(Direct Programming Interface) and Scemi pipes that allow the inter language function calls between SystemVerilog and C language.
  • Gained knowledge on SystemVerilog, UVM and Perl, successfully completed tasks assigned.
Emulation toolsPower aware analysisSystemVerilogUVMPerlVerification+1

Education

Birla Institute of Technology and Science, Pilani

Master of Engineering (M.Eng.) — Microelectronics

Jan 2011 – Jan 2013

Cvr College Of Engineering

Bachelor of Technology (B.Tech.) — Electronics and Communication Engineering

Jan 2007 – Jan 2011

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