Neha Pachauri — Engineering Manager

Owning multiple chiplets and driving them for full closure including Design Planning, PNR, IR, timing. Full ownership of blocks from RTL to GDSII (Synthesis , floorplanning, PNR, timing and SI analysis/closure, parasitic extraction, ECO tasks; both functional and timing, EM/IR, DRC, LVS, ERC analysis and fixes) Worked on sub-FC PnR. Participated in flow automation and improvements on existing PNR flow to increase efficiency Working knowledge of deep-submicron issues Provide technical coaching and mentoring to junior team members and others when necessary to achieve successful project outcomes Worked as D&I Champion with IDAN ( Intel Diverse Ability Network)

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and Physical Design.

Location: Bengaluru, Karnataka, India

Experience: 12 yrs 2 mos